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ST72F521 Datasheet(PDF) 34 Page - STMicroelectronics |
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ST72F521 Datasheet(HTML) 34 Page - STMicroelectronics |
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34 / 215 page  ST72F521, ST72521B 34/215 INTERRUPTS (Cont’d) Servicing Pending Interrupts As several interrupts can be pending at the same time, the interrupt to be taken into account is deter- mined by the following two-step process: – the highest software priority interrupt is serviced, – if several interrupts have the same software pri- ority then the interrupt with the highest hardware priority is serviced first. Figure 19 describes this decision process. Figure 19. Priority Decision Process When an interrupt request is not serviced immedi- ately, it is latched and then processed when its software priority combined with the hardware pri- ority becomes the highest one. Note 1: The hardware priority is exclusive while the software one is not. This allows the previous process to succeed with only one interrupt. Note 2: TLI, RESET and TRAP can be considered as having the highest software priority in the deci- sion process. Different Interrupt Vector Sources Two interrupt source types are managed by the ST7 interrupt controller: the non-maskable type (RESET, TRAP) and the maskable type (external or from internal peripherals). Non-Maskable Sources These sources are processed regardless of the state of the I1 and I0 bits of the CC register (see Figure 18). After stacking the PC, X, A and CC registers (except for RESET), the corresponding vector is loaded in the PC register and the I1 and I0 bits of the CC are set to disable interrupts (level 3). These sources allow the processor to exit HALT mode. ■ TRAP (Non Maskable Software Interrupt) This software interrupt is serviced when the TRAP instruction is executed. It will be serviced accord- ing to the flowchart in Figure 18. Caution: TRAP can be interrupted by a TLI. ■ RESET The RESET source has the highest priority in the ST7. This means that the first current routine has the highest software priority (level 3) and the high- est hardware priority. See the RESET chapter for more details. Maskable Sources Maskable interrupt vector sources can be serviced if the corresponding interrupt is enabled and if its own interrupt software priority (in ISPRx registers) is higher than the one currently being serviced (I1 and I0 in CC register). If any of these two condi- tions is false, the interrupt is latched and thus re- mains pending. ■ TLI (Top Level Hardware Interrupt) This hardware interrupt occurs when a specific edge is detected on the dedicated TLI pin. It will be serviced according to the flowchart in Figure 18 as a trap. Caution: A TRAP instruction must not be used in a TLI service routine. ■ External Interrupts External interrupts allow the processor to exit from HALT low power mode. External interrupt sensitiv- ity is software selectable through the External In- terrupt Control register (EICR). External interrupt triggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine. If several input pins of a group connected to the same interrupt line are selected simultaneously, these will be logically ORed. ■ Peripheral Interrupts Usually the peripheral interrupts cause the MCU to exit from HALT mode except those mentioned in the “Interrupt Mapping” table. A peripheral inter- rupt occurs when a specific flag is set in the pe- ripheral status registers and if the corresponding enable bit is set in the peripheral control register. The general sequence for clearing an interrupt is based on an access to the status register followed by a read or write to an associated register. Note: The clearing sequence resets the internal latch. A pending interrupt (i.e. waiting for being serviced) will therefore be lost if the clear se- quence is executed. PENDING SOFTWARE Different INTERRUPTS Same HIGHEST HARDWARE PRIORITY SERVICED PRIORITY HIGHEST SOFTWARE PRIORITY SERVICED |
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