M48T35AV

Operation modes

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Table 4.

Write mode AC characteristics

2.3

Data retention mode

RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write

Table 10, and Table 11 on page 21). All outputs become high impedance, and all inputs are

treated as “don't care.”

Note:

A power failure during a WRITE cycle may corrupt data at the currently addressed location,

of the power supply lines is recommended.

preserves data and powers the clock. The internal button cell will maintain data in the

Symbol

1.

M48T35AV

Unit

Min

Max

WRITE cycle time

100

ns

Address valid to WRITE enable low

0

ns

Address valid to chip enable low

0

ns

WRITE enable pulse width

80

ns

Chip enable low to chip enable high

80

ns

WRITE enable high to address transition

10

ns

Chip enable high to address transition

10

ns

Input valid to WRITE enable high

50

ns

Input valid to chip enable high

50

ns

WRITE enable high to input transition

5

ns

Chip enable high to input transition

5

ns

(2)(3)

2.

3.

If E goes low simultaneously with W going low, the outputs remain in the high impedance state.

WRITE enable low to output Hi-Z

50

ns

Address valid to WRITE enable high

80

ns

Address valid to chip enable high

80

ns

(2)(3)

WRITE enable high to output transition

10

ns