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P10C68-45DCBS Datasheet(PDF) 5 Page - Zarlink Semiconductor Inc |
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P10C68-45DCBS Datasheet(HTML) 5 Page - Zarlink Semiconductor Inc |
5 / 17 page P10C68/P11C68 5 SRAM MEMORY OPERATION Test conditions (unless otherwise stated): Commercial and Industrial Temperature Range Tamb = -40°C to + 85°C, Vcc = + 5V ± 10% READ CYCLES 1 AND 2 (See note 8) NOTES 8. E (bar), G (bar) and W (bar) must make the transition between VIH(min) to VIL(max), or VIL(max) to VIH(min) in a monotonic fashion. NE (bar) must be ≥ VIH during entire cycle. 9. For READ CYCLE 1 and 2, W (bar) and NE (bar) must be high for entire cycle. 10. Device is continuously selected with E (bar) low, and G (bar) low. 11. Measured ±200mV from steady state output voltage. Load capacitance is 5pF. 12. Parameter guaranteed but not tested. tAVAV tAVQV tAXQX tWHQV ADDRESS DQ (DATA OUT) W DATA VALID Figure 4. READ CYCLE 1 timing diagram (see notes 9 and 10). Standard tELQV tAVAV tAVQV tGLQV tAXQX tELQX tEHQZ tGLQX tGHQZ tELICCH tEHICCL tWHQV Alternative tACS tRC tAA tOE tOH tLZ tOHZ tOLZ tHZ tPA tPS tWR Parameter Chip enable access time Read cycle time Address access time Output enable to data valid Output hold after address change Chip enable to output active Chip disable to output inactive Output enable to output active Outout disable to output inactive Chip enable to power active Chip disable to power standby Write recovery time Units ns ns ns ns ns ns ns ns ns ns ns ns Notes 9 10 11 11 12 12 P10C68-45 P11C68-45 P10C68-35 P11C68-35 Symbol Min. 45 5 5 0 0 Max. 45 45 25 25 20 25 55 Min. 35 5 5 0 0 Max. 35 35 20 20 15 25 45 |
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