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PCA9543APW Datasheet(PDF) 7 Page - Texas Instruments |
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PCA9543APW Datasheet(HTML) 7 Page - Texas Instruments |
7 / 20 page www.ti.com S 1 2 8 9 NACK ACK DataOutput byTransmitter DataOutput byReceiver SCL From Master Start Condition ClockPulsefor Acknowledgment SDA Slave Address ControlRegister Stop Condition R/W Start Condition Acknowledge FromSlave Acknowledge FromSlave A1 S A0 1 1 1 0 0 0 A A P X X X X X X B1 B0 SDA Slave Address ControlRegister Stop Condition R/W Start Condition No Acknowledge FromMaster Acknowledge FromSlave LastByte A1 S A0 1 1 1 0 0 1 A NA P X X INT1 INT0 X X B1 B0 PCA9543A TWO-CHANNEL I2C-BUS SWITCH WITH INTERRUPT LOGIC AND RESET SCPS169 – SEPTEMBER 2007 When a slave receiver is addressed, it must generate an ACK after the reception of each byte. Also, a master must generate an ACK after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges must pull down the SDA line during the ACK clock pulse, so that the SDA line is stable low during the high pulse of the ACK-related clock period (see Figure 8). Setup and hold times must be taken into account. A master receiver must signal an end of data to the transmitter by not generating an acknowledge (NACK) after the last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line high. In this event, the transmitter must release the data line to enable the master to generate a stop condition. Figure 8. Acknowledgment on I2C Bus Data is transmitted to the PCA9543A control register using the write mode shown in Figure 9. Figure 9. Write Control Register Data is read from the PCA9543A control register using the read mode shown in Figure 10. Figure 10. Read Control Register Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Link(s): PCA9543A |
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