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ISPPAC-POWR1014A Datasheet(PDF) 10 Page - Lattice Semiconductor |
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ISPPAC-POWR1014A Datasheet(HTML) 10 Page - Lattice Semiconductor |
10 / 45 page Lattice Semiconductor ispPAC-POWR1014/A Data Sheet 10 I 2C Port Characteristics1 Symbol Definition 100KHz 400KHz Units Min. Max. Min. Max. FI2C I 2C clock/data rate 100 2 400 2 KHz TSU;STA After start 4.7 0.6 us THD;STA After start 4 0.6 us TSU;DAT Data setup 250 100 ns TSU;STO Stop setup 4 0.6 us THD;DAT Data hold; SCL= Vih_min = 2.1V 0.3 3.45 0.3 0.9 us TLOW Clock low period 4.7 10 1.3 10 us THIGH Clock high period 4 0.6 us TF Fall time; 2.25V to 0.65V 300 300 ns TR Rise time; 0.65V to 2.25V 1000 300 ns TTIMEOUT Detect clock low timeout 25 35 25 35 ms TPOR Device must be operational after power-on reset 500 500 ms TBUF Bus free time between stop and start condition 4.7 1.3 us 1. Applies to ispPAC-POWR1014A only. 2. If FI2C is less than 50kHz, then the ADC DONE status bit is not guaranteed to be set after a valid conversion request is completed. In this case, waiting for the TCONVERT minimum time after a convert request is made is the only way to guarantee a valid conversion is ready for readout. When FI2C is greater than 50kHz, ADC conversion complete is ensured by waiting for the DONE status bit. |
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Similar Description - ISPPAC-POWR1014A |
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