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SN65LVDS250 Datasheet(PDF) 6 Page - Texas Instruments |
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SN65LVDS250 Datasheet(HTML) 6 Page - Texas Instruments |
6 / 18 page www.ti.com OUTPUT ELECTRICAL CHARACTERISTICS SWITCHING CHARACTERISTICS SN65LVDS250 SN65LVDT250 SLLS594B – MARCH 2004 – REVISED OCTOBER 2004 over recommended operating conditions unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT |VOD| Differential output voltage magnitude 247 350 454 mV See Figure 2 VID = ±100 mV ∆|V OD| Change in differential output voltage magnitude between logic states -50 50 mV VOC(SS) Steady-state common-mode output voltage 1.125 1.375 V Change in steady-state common-mode output voltage between logic ∆V OC(SS) See Figure 3 -50 50 mV states VOC(PP) Peak-to-peak common-mode output voltage 50 150 mV ICC Supply current RL=100 Ω 110 145 mA IOS Short-circuit output current VOY or VOZ = 0 V -27 27 mA IOSD Differential short circuit output current VOD = 0 V -12 12 mA IOZ High-impedance output current VO = 0 V or VCC ±1 µA CO Differential output capacitance 2 pF over recommended operating conditions unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tPLH Propagation delay time, low-to-high-level output 700 800 1200 tPHL Propagation delay time, high-to-low-level output 700 800 1200 See Figure 4 ps tr Differential output signal rise time (20%-80%) 200 245 tf Differential output signal fall time (20%-80%) 200 245 tsk(p) Pulse skew (|tPHL - tPLH|)(1) 0 50 ps tsk(o) Channel-to-channel output skew(2) 175 ps tsk(pp) Part-to-part skew(3) 300 ps tjit(per) Period jitter, rms (1 standard deviation)(4) See Figure 6 1 3 ps tjit(cc) Cycle-to-cycle jitter (peak)(5) See Figure 6 8 17 ps tjit(pp) Peak-to-peak jitteR(6) See Figure 6 60 110 ps tjit(det) Deterministic jitter, peak-to-peak(7) See Figure 6 48 65 ps tPHZ Propagation delay, high-level-to-high-impedance output 6 tPLZ Propagation delay, low-level-to-high-impedance output 6 See Figure 5 ns tPZH Propagation delay, high-impedance -to-high-level output 300 tPZL Propagation delay, high-impedance-to-low-level output 300 (1) tsk(p) is the magnitude of the time difference between the tPLH and tPHL of any output of a single device. (2) tsk(o) is the maximum delay time difference between drivers over temperature, VCC, and process. (3) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. (4) Input voltage = VID = 200 mV, 50% duty cycle at 1.0 GHz, tr = tf= 50 ps (20% to 80%), measured over 1000 samples. (5) Input voltage = VID = 200 mV, 50% duty cycle at 1.0 GHz, tr = tf= 50 ps (20% to 80%). (6) Input voltage = VID = 200 mV, 223-1 PRBS pattern at 2.0 Gbps, tr = tf = 50 ps (20% to 80%), measured over 200k samples. (7) Input voltage = VID = 200 mV, 27-1 PRBS pattern at 2.0 Gbps, tr= tf = 50 ps (20% to 80%). 6 |
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