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TC74HCT139AF Datasheet(PDF) 1 Page - Toshiba Semiconductor |
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TC74HCT139AF Datasheet(HTML) 1 Page - Toshiba Semiconductor |
1 / 8 page TC74HCT139AP/AF/AFN 2007-10-01 1 TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HCT139AP,TC74HCT139AF,TC74HCT139AFN Dual 2-to-4 Line Decoder The TC74HCT139A is a high speed CMOS 2-to-4 LINE DECODER/DEMULTIPLEXER fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. This device may be used as a level converter for interfacing TTL or NMOS to High Speed CMOS. The inputs are compatible with TTL, NMOS and CMOS output voltage levels. The active low enable input can be used for gating or it can be used as a data input for demultiplexing applications. When the enable input is held “H”, all four outputs are fixed at a high logic level independent of the other inputs. All inputs are equipped with protection circuits against static discharge or transient excess voltage. Features • High speed: tpd = 17 ns (typ.) at VCC = 5 V • Low power dissipation: ICC = 4 μA (max) at Ta = 25°C • Compatible with TTL outputs: VIH = 2 V (min) VIL = 0.8 V (max) • Wide interfacing ability: LSTTL, NMOS, CMOS • Output drive capability: 10 LSTTL loads • Symmetrical output impedance: |IOH| = IOL = 4 mA (min) • Balanced propagation delays: tpLH ∼− tpHL • Pin and function compatible with 74LS139 Pin Assignment Note: xxxFN (JEDEC SOP) is not available in Japan. TC74HCT139AP TC74HCT139AF TC74HCT139AFN Weight DIP16-P-300-2.54A : 1.00 g (typ.) SOP16-P-300-1.27A : 0.18 g (typ.) SOL16-P-150-1.27 : 0.13 g (typ.) |
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