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R1LV1616HBG-4SI Datasheet(PDF) 7 Page - Renesas Technology Corp |
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R1LV1616HBG-4SI Datasheet(HTML) 7 Page - Renesas Technology Corp |
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7 / 15 page  R1LV1616HBG-I Series Rev.1.00, Sep.21.2005, page 7 of 13 Read Cycle R1LV1616HBG-I -4SI -5SI Parameter Symbol Min Max Min Max Unit Notes Read cycle time tRC 45 55 ns Address access time tAA 45 55 ns Chip select access time tACS1 45 55 ns tACS2 45 55 ns Output enable to output valid tOE 30 35 ns Output hold from address change tOH 10 10 ns LB#, UB# access time tBA 45 55 ns Chip select to output in low-Z tCLZ1 10 10 ns 2, 3 tCLZ2 10 10 ns 2, 3 LB#, UB# enable to low-Z tBLZ 5 5 ns 2, 3 Output enable to output in low-Z tOLZ 5 5 ns 2, 3 Chip deselect to output in high-Z tCHZ1 0 20 0 20 ns 1, 2, 3 tCHZ2 0 20 0 20 ns 1, 2, 3 LB#, UB# disable to high-Z tBHZ 0 15 0 20 ns 1, 2, 3 Output disable to output in high-Z tOHZ 0 15 0 20 ns 1, 2, 3 Write Cycle R1LV1616HBG-I -4SI -5SI Parameter Symbol Min Max Min Max Unit Notes Write cycle time tWC 45 55 ns Address valid to end of write tAW 45 50 ns Chip selection to end of write tCW 45 50 ns 5 Write pulse width tWP 35 40 ns 4 LB#, UB# valid to end of write tBW 45 50 ns Address setup time tAS 0 0 ns 6 Write recovery time tWR 0 0 ns 7 Data to write time overlap tDW 25 25 ns Data hold from write time tDH 0 0 ns Output active from end of write tOW 5 5 ns 2 Output disable to output in high-Z tOHZ 0 15 0 20 ns 1, 2 Write to output in high-Z tWHZ 0 15 0 20 ns 1, 2 Notes: 1. tCHZ, tOHZ, tWHZ and tBHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2. This parameter is sampled and not 100% tested. 3. At any given temperature and voltage condition, tHZ max is less than tLZ min both for a given device and from device to device. 4. A write occurs during the overlap of a low CS1#, a high CS2, a low WE# and a low LB# or a low UB#. A write begins at the latest transition among CS1# going low, CS2 going high, WE# going low and LB# going low or UB# going low. A write ends at the earliest transition among CS1# going high, CS2 going low, WE# going high and LB# going high or UB# going high. tWP is measured from the beginning of write to the end of write. 5. tCW is measured from the later of CS1# going low or CS2 going high to the end of write. 6. tAS is measured from the address valid to the beginning of write. 7. tWR is measured from the earliest of CS1# or WE# going high or CS2 going low to the end of write cycle. |
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