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TC74AC112P Datasheet(PDF) 5 Page - Toshiba Semiconductor

Part No. TC74AC112P
Description  CMOS Digital Integrated Circuit Silicon Monolithic Dual J-K Flip Flop with Preset and Clear
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Maker  TOSHIBA [Toshiba Semiconductor]
Homepage  http://www.semicon.toshiba.co.jp/eng
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TC74AC112P Datasheet(HTML) 5 Page - Toshiba Semiconductor

   
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TC74AC112P/F/FN
2007-10-01
5
Timing Requirements (input: tr = tf = 3 ns)
Test Condition
Ta
=
25°C
Ta
=
−40 to
85°C
Characteristics
Symbol
VCC (V)
Limit
Limit
Unit
Minimum pulse width
(
CK )
tW (L)
tW (H)
3.3
± 0.3
5.0
± 0.5
7.5
5.0
7.5
5.0
ns
Minimum pulse width
( CLR , PR )
tW (L)
3.3
± 0.3
5.0
± 0.5
7.0
5.0
7.0
5.0
ns
Minimum set-up time
ts
3.3
± 0.3
5.0
± 0.5
11.0
6.0
11.0
6.0
ns
Minimum hold time
th
3.3
± 0.3
5.0
± 0.5
0.0
0.0
0.0
0.0
ns
Minimum removal time
( CLR , PR )
trem
3.3
± 0.3
5.0
± 0.5
3.0
2.0
3.0
2.0
ns
AC Characteristics (CL = 50 pF, RL = 500 Ω, input: tr = tf = 3 ns)
Test Condition
Ta
= 25°C
Ta
= −40 to
85°C
Characteristics
Symbol
VCC (V)
Min
Typ.
Max
Min
Max
Unit
Propagation delay
time
( CK -Q, Q )
tpLH
tpHL
3.3
± 0.3
5.0
± 0.5
9.1
6.5
15.5
9.4
1.0
1.0
17.8
10.8
ns
Propagation delay
time
( CLR , PR -Q, Q)
tpLH
tpHL
3.3
± 0.3
5.0
± 0.5
8.6
5.8
14.6
8.3
1.0
1.0
16.8
9.6
ns
Maximum clock
frequency
fmax
3.3
± 0.3
5.0
± 0.5
45
80
90
150
45
80
MHz
Input capacitance
CIN
5
10
10
pF
Power dissipation
capacitance
CPD
(Note)
85
pF
Note:
CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating
current consumption without load.
Average operating current can be obtained by the equation:
ICC (opr) = CPD・VCC・fIN + ICC/2 (per F/F)


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