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TC74AC109P Datasheet(PDF) 1 Page - Toshiba Semiconductor

Part No. TC74AC109P
Description  CMOS Digital Integrated Circuit Silicon Monolithic Dual J-K Flip Flop with Preset and Clear
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Maker  TOSHIBA [Toshiba Semiconductor]
Homepage  http://www.semicon.toshiba.co.jp/eng
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TC74AC109P Datasheet(HTML) 1 Page - Toshiba Semiconductor

   
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TC74AC109P/F/FN
2007-10-01
1
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC74AC109P,TC74AC109F,TC74AC109FN
Dual J-K Flip Flop with Preset and Clear
The TC74AC109 is an advanced high speed CMOS DUAL J-
K
FLIP FLOP fabricated with silicon gate and double-layer metal
wiring C2MOS technology.
It achieves the high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low power
dissipation.
In accordance with the logic level given J and K input this
device changes state on positive going transition of the clock
pulse. CLEAR and PRESET are independent of the clock and
accomplished by a low logic level on the corresponding input.
All inputs are equipped with protection circuits against static
discharge or transient excess voltage.
Features
• High speed: fmax = 200 MHz (typ.) at VCC = 5 V
• Low power dissipation: ICC = 4 μA (max) at Ta = 25°C
• High noise immunity: VNIH = VNIL = 28% VCC (min)
• Symmetrical output impedance: |IOH| = IOL = 24 mA (min)
Capability of driving 50
Ω
transmission lines.
• Balanced propagation delays: tpLH ∼− tpHL
• Wide operating voltage range: VCC (opr) = 2 to 5.5 V
• Pin and function compatible with 74F109
Pin Assignment
Note:
xxxFN (JEDEC SOP) is not available in
Japan.
TC74AC109P
TC74AC109F
TC74AC109FN
Weight
DIP16-P-300-2.54A
: 1.00 g (typ.)
SOP16-P-300-1.27A
: 0.18 g (typ.)
SOL16-P-150-1.27
: 0.13 g (typ.)


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