TC9WMC1FK/FU,TC9WMC2FK/FU

2007-10-19

2

Block Diagram

Pin Function

Pin Name

Input/Output

Function

CS

Input

Chip select input

The device receives an instruction set when this pin is driven High.

This pin must be driven Low before execution of an instruction.

SK

Input

Serial clock input

Data is latched on the rising edge of SK. Data is transferred on the rising edge of SK.

This pin is valid when CS is driven High.

DI

Input

Serial data input (start bit, op code, address and data)

DO

Output

Serial data output

TEST

Input

Test mode input (internal pull-down resistor)

Normally kept open. (Can be connected to GND.)

NC

⎯

No connection (not connected internally)

1.8 to 3.6 V (for reading)

2.3 to 3.6 V (for writing)

GND

Power supply

0 V (GND)

Control

circuit

Power supply

(booster circuit)

Memory cell

Data register

Timing

generator

Address

register

Input/output

circuit

GND

Command

register

Clock input: SK

Chip select: CS

Address

decoder

Data input: DI

Data output: DO

Test input

TEST