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TMP86CH06AUG Datasheet(PDF) 36 Page - Toshiba Semiconductor |
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TMP86CH06AUG Datasheet(HTML) 36 Page - Toshiba Semiconductor |
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36 / 158 page  Page 26 2. Operational Description 2.1 CPU Core Functions TMP86CH06AUG (c) Normal release mode (IMF = “0”) IDLE1/2 and SLEEP1/2 modes are released by any interrupt source enabled by the individual interrupt enable flag (EF). After the interrupt is generated, the program operation is resumed from the instruction following the IDLE1/2 and SLEEP1/2 modes start instruction. Normally, the interrupt latches (IL) of the interrupt source used for releasing must be cleared to “0” by load instructions. (d) Interrupt release mode (IMF = “1”) IDLE1/2 and SLEEP1/2 modes are released by any interrupt source enabled with the individ- ual interrupt enable flag (EF) and the interrupt processing is started. After the interrupt is pro- cessed, the program operation is resumed from the instruction following the instruction, which starts IDLE1/2 and SLEEP1/2 modes. Note: When a watchdog timer interrupts is generated immediately before IDLE1/2 and SLEEP1/2 mode are started, the watchdog timer interrupt will be processed but IDLE1/2 and SLEEP1/2 mode will not be started. |
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