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SSM3J15CT Datasheet(PDF) 1 Page - Toshiba Semiconductor |
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SSM3J15CT Datasheet(HTML) 1 Page - Toshiba Semiconductor |
1 / 5 page SSM3J15CT 2007-11-01 1 TOSHIBA Field Effect Transistor Silicon P-Channel MOS Type SSM3J15CT High-Speed Switching Applications Analog Switch Applications • Optimum for high-density mounting in small packages • Low ON-resistance : Ron = 12 Ω (max) (@VGS = −4 V) : Ron = 32 Ω (max) (@VGS = −2.5 V) Absolute Maximum Ratings (Ta = 25°C) Characteristics Symbol Rating Unit Drain-Source voltage VDS −30 V Gate-Source voltage VGSS ±20 V DC ID −100 Drain current Pulse IDP −200 mA Drain power dissipation (Ta = 25°C) PD (Note 1) 100 mW Channel temperature Tch 150 °C Storage temperature range Tstg −55~150 °C Note: Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook (“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test report and estimated failure rate, etc). Note 1: Mounted on an FR4 board (10 mm × 10 mm × 1.0 t, Cu Pad: 100 mm 2 ) Marking (Top View) Pin Condition (Top View) Equivalent Circuit Handling Precaution When handling individual devices that are not yet mounted on a circuit board, ensure that the environment is protected against electrostatic discharge. Operators should wear anti-static clothing, and containers and other objects that come into direct contact with devices should be made of anti-static materials. Unit: mm JEDEC - JEITA - TOSHIBA 2-1J1B Weight: 0.75 mg (typ.) CST3 3 12 0.35±0.02 0.15±0.03 0.5±0.03 0.6±0.05 0.05±0.03 1. Gate 2. Source 3. Drain *Electrodes: on the bottom Polarity mark Polarity mark (on the top) 1 2 3 S1 12 3 |
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