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TMP86FS49BUG Datasheet(PDF) 85 Page - Toshiba Semiconductor |
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TMP86FS49BUG Datasheet(HTML) 85 Page - Toshiba Semiconductor |
85 / 294 page Page 69 TMP86FS49BUG 6.2.5 Watchdog Timer Reset When a binary-counter overflow occurs while WDTCR1<WDTOUT> is set to “1”, a watchdog timer reset request is generated. When a watchdog timer reset request is generated, the internal hardware is reset. The reset time is maximum 24/fc [s] (1.5 µs @ fc = 16.0 MHz). Note:When a watchdog timer reset is generated in the SLOW1 mode, the reset time is maximum 24/fc (high-fre- quency clock) since the high-frequency clock oscillator is restarted. However, when crystals have inaccura- cies upon start of the high-frequency clock oscillator, the reset time should be considered as an approximate value because it has slight errors. Figure 6-2 Watchdog Timer Interrupt Clock Binary counter Overflow INTWDT interrupt request (WDTCR1<WDTOUT>= "0") 217/fc 219/fc [s] (WDTT=11) Write 4EH to WDTCR2 1 2 30 1 2 3 0 Internal reset (WDTCR1<WDTOUT>= "1") A reset occurs |
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