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TMP88CH41UG Datasheet(PDF) 77 Page - Toshiba Semiconductor |
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TMP88CH41UG Datasheet(HTML) 77 Page - Toshiba Semiconductor |
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77 / 186 page  Page 67 TMP88CH41UG Example :Duty measurement (resolution fc/27 [Hz], CGCR<DV1CK> = “0”) CLR (INTTC1SW). 0 ; INTTC1 service switch initial setting Address set to convert INTTC1SW at each INTTC1 LD (TC1CR), 00000110B ; Sets the TC1 mode and source clock DI ; IMF = “0” SET (EIRD). 2 ; Enables INTTC1 EI ; IMF = “1” LD (TC1CR), 00100110B ; Starts TC1 with an external trigger at MCAP1 = 0 : PINTTC1: CPL (INTTC1SW). 0 ; INTTC1 interrupt, inverts and tests INTTC1 service switch JRS F, SINTTC1 LD A, (TC1DRBL) ; Reads TC1DRB (High-level pulse width) LD W,(TC1DRBH) LD (HPULSE), WA ; Stores high-level pulse width in RAM RETI SINTTC1: LD A, (TC1DRBL) ; Reads TC1DRB (Cycle) LD W,(TC1DRBH) LD (WIDTH), WA ; Stores cycle in RAM : RETI ; Duty calculation : VINTTC1: DW PINTTC1 ; INTTC1 Interrupt vector WIDTH HPULSE TC1 pin INTTC1 interrupt request INTTC1SW |
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