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TMP88CH41NG Datasheet(PDF) 17 Page - Toshiba Semiconductor |
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TMP88CH41NG Datasheet(HTML) 17 Page - Toshiba Semiconductor |
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17 / 186 page  Page 7 TMP88CH41NG 2. Functional Description 2.1 Functions of the CPU Core The CPU core consists mainly of the CPU, system clock control circuit, and interrupt control circuit. This chapter describes the CPU core, program memory, data memory, and reset circuit of the TMP88CH41NG. 2.1.1 Memory Address Map The memory of the TMP88CH41NG consists of four blocks: ROM, RAM, SFR (Special Function Regis- ters), and DBR (Data Buffer Registers), which are mapped into one 1-Mbyte address space. The general-pur- pose registers consist of 16 banks, which are mapped into the RAM address space. Figure 2-1 shows a memory address map of the TMP88CH41NG. Figure 2-1 Memory address map Vector Table for Vector Call Instructions Interrupt Vector Table Interrupt Vector Table Program Memory ROM ( Kbytes) RAM ( bytes) RAM (128 bytes) SFR ROM: Read-Only Memory Program memory Vector Table SFR: Special Function Registers Input/output port Peripheral hardware control register Peripheral hardware status register System control register Interrupt control register Program status word DBR: Data Buffer Registers Input/output port Peripheral hardware control register Peripheral hardware status register RAM: Random Access Memory Data memory Stack General-purpose register bank Random-Access Memory Special Function Register General-purpose Register Bank (8 registers × 16 banks) Data Buffer Register (peripheral hardware control register / status register) 64 bytes 64 bytes 64 bytes 128 bytes bytes bytes 128 bytes 00000H 000C0H 000BFH 04000H 0003FH 00040H 01FFFH FFFFFH FFF7FH FFF80H FFF40H FFF00H FFF3FH bytes 512 512 16K 16128 DBR 01F80H 07EFFH 002BFH 128 |
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