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Floating Point Pipelined Multiplier Unit

ver 2.70

OVERVIEW

The DFPMUL uses the pipelined mathemat-

ics algorithm to multiply two arguments. The

input numbers format is according to IEEE-

754 standard. DFPMUL supports single pre-

cision real number. Multiply operation was

pipelined up to 7 levels. Input data are fed

every clock cycle. The first result appears

after latency depending on pipeline level and

next results are available each clock cycle.

Full IEEE-754 precision and accuracy were

included.

APPLI C ATION

Math coprocessors

DSP algorithms

Embedded arithmetic coprocessor

Data processing & control

KEY FEATURES

Full IEEE-754 compliance

Single precision real format support

Simple interface

No programming required

7 levels pipeline

Full accuracy and precision

Overflow, underflow and invalid operation

flags

Results available at every clock

Fully configurable

Fully synthesizable, static synchronous

design with no internal tri-states

DELIVERABLES

Source code:

VHDL Source Code or/and

VERILOG Source Code or/and

EDIF netlist

VHDL & VERILOG test bench environ-

ment

Active-HDL automatic simulation mac-

ros

NCSim automatic simulation macros

ModelSim automatic simulation macros

Tests with reference responses

Technical documentation

Installation notes

HDL core specification

Datasheet

Synthesis scripts

Example application

Technical support

IP Core implementation support

3 months maintenance

●

Delivery the IP Core updates, minor

and major versions changes

●

Delivery the documentation updates

●

Phone & email support

LICENSING

Comprehensible and clearly defined licensing

methods without royalty fees make using of

IP Core easy and simply.

Single Design

license allows using IP Core in

single FPGA bitstream and ASIC implemen-