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DF6811CPU Datasheet(PDF) 5 Page - Digital Core Design |
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DF6811CPU Datasheet(HTML) 5 Page - Digital Core Design |
5 / 7 page All trademarks mentioned in this document are trademarks of their respective owners. Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved. ○ ○ ● ○ ○ ○ ○ ● ○ ○ ○ ○ ○ ○ ○ ○ ● ○ ○ ○ ○ ○ ● ○ ○ ○ ● ○ ○ ○ ○ ○ ○ ○ ● ○ ○ ○ ○ ○ ○ ● ● ○ ○ ○ ○ ○ ● ○ ○ ○ ○ ○ ○ ● ○ ○ ○ ○ ○ ○ ○ ○ http://www.DigitalCoreDesign.com http://www.dcd.pl Pulse width modulation Pulse width measuring 8-bit Pulse accumulator Two major modes of operation Simple event counter Gated time accumulation Clocked by internal source or external pin Full-duplex UART - SCI Standard Nonreturn to Zero format (NRZ) 8 or 9 bit data transfer Integrated baud rate generator Enhanced receiver data sampling technique Noise, Overrun and Framing error detection IDLE and BREAK characters generation Wake-up block to recognize UART wake-up from IDLE condition Three SCI related interrupts SPI – Master and Slave Serial Peripheral Interface Supports speeds up ¼ of system clock Software selectable polarity and phase of se- rial clock SCK System errors detection Allows operation from a wide range of system clock frequencies (build-in 5-bit timer) Interrupt generation PWM – Pulse Width Modulation Timer 4 independent 8-bit PWM channels, concate- nated on two 16-bit PWM channel Software-selectable duty from 0% to 100% and pulse period Software-selectable polarity of output wave- form I2C bus controller - Master 7-bit and 10-bit addressing modes NORMAL, FAST, HIGH speeds Multi-master systems supported Clock arbitration and synchronization User defined timings on I2C lines Wide range of system clock frequencies Interrupt generation I2C bus controller - Slave NORMAL speed 100 kbs FAST speed 400 kbs HIGH speed 3400 kbs Wide range of system clock frequencies User defined data setup time on I2C lines Interrupt generation Programmable Watchdog Timer Fixed-Point arithmetic coprocessor Multiplication - 16bit * 16bit Division - 32bit / 16bit Division - 16bit / 16bit Left and right shifting - 1 to 31 bits Normalization Floating-Point arithmetic coprocessor IEEE-754 standard single precision FADD, FSUB - addition, subtraction FMUL, FDIV- multiplication, division FSQRT- square root FUCOM - compare FCHS - change sign FABS - absolute value Floating-Point math coprocessor - IEEE- 754 standard single precision real, word and short integers FADD, FSUB- addition, subtraction FMUL, FDIV- multiplication, division FSQRT- square root FUCOM- compare FCHS - change sign FABS - absolute value FSIN, FCOS- sine, cosine FTAN, FATAN – tangent arcs tangent |
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