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D16750 Datasheet(PDF) 4 Page - Digital Core Design

Part # D16750
Description  Configurable UART with FIFO
Download  7 Pages
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Manufacturer  DCD [Digital Core Design]
Direct Link  http://www.digitalcoredesign.com
Logo DCD - Digital Core Design

D16750 Datasheet(HTML) 4 Page - Digital Core Design

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All trademarks mentioned in this document
are trademarks of their respective owners.
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.
http://www.DigitalCoreDesign.com
http://www.dcd.pl
SYMBOL
datai(7:0)
address(2:0)
datao(7:0)
so
rts
dtr
out1
out2
cts
dsr
dcd
ri
wr
rd
cs
si
rst
clk
rclk
baudclk
baudout
intr
ddis
txrdy
rxrdy
D16750
baudclken
rclken
PINS DESCRIPTI O N
PIN
TYPE
DESCRIPTION
rst
input
Global reset
clk
input
Global clock
datai[7:0]
input
Parallel data input
addr[2:0]
input
Address bus
cs
input
Chip select input
wr
input
Write input
rd
input
Read input
rclk
input
Receiver clock
baudclk
input
Baud generator clock
si
input
Serial data input
cts
input
Clear to send input
dsr
input
Data set ready input
dcd
input
Data carrier detect input
ri
input
Ring indicator input
baudclken
input
Baud generator clock enable
rclken
input
Receiver clock enable
baudout
output
Baud generator output
datao[7:0]
output
Parallel data output
so
output
Serial data output
ddis
output
Driver disable output
txrdy
output
Transmitter ready output
rxrdy
output
Receiver ready output
rts
output
Request to send output
dtr
output
Data terminal ready output
out1
output
Output 1
out2
output
Output 2
intr
output
Interrupt request output
Note
: When enabled RCLK and BAUDCLK pins
frequency should be at least two times lower
than CLK, 2*fRCLK< fCLK
APPLI C ATION
D16750
addr(2:0)
addr
latch
datai(7:0)
datao(7:0)
wr
rd
cs
intr
rxrdy
txrdy
out1
out2
EIA
Drivers
so
si
rts
dtr
dsr
dcd
cts
ri
baudclken
rclken
clk
rst
baudclk
rclk
CPU
addr
ale
datao(7:0)
datai(7:0)
we
rd
cs
int
Typical D16750 and processor connection is
shown in figure above.
BLOCK DIAGRAM
Data Bus Buffer
- The data Bus Buffer
accepts inputs from the system bus and
generates control signals for the other D16750
functional blocks. Address bus ADDR(2:0)
selects one of the register to be read
from/written into. Both RD and WE signals are
active low, and are qualified by CS; RD and
WE are ignored unless the D16750 has been
selected by holding CS low.
Baud Generator
- The D16750 contains a
programmable 16 bit baud generator that
divides clock input by a divisor in the range
between 1 and (216–1). The output frequency
of the baud generator is 16× the baud rate.
The formula for the divisor is:
16
*
baudrate
frequency
divisor
=
Two 8-bit registers, called divisor latches DLL
and DLM, store the divisor in a 16-bit binary
format. These divisor latches must be loaded
during initialization of the D16750 in order to
ensure
desired
operation
of
the
baud
generator. When either of the divisor latches
is loaded, a 16-bit baud counter is also loaded
on the CLK rising edge following the write to
DLL or DLM to prevent long counts on initial
load.
Modem Control Logic
controls the interface
with the MODEM or data set (or a peripheral
device emulating a MODEM).


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