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D16750 Datasheet(PDF) 3 Page - Digital Core Design

Part # D16750
Description  Configurable UART with FIFO
Download  7 Pages
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Manufacturer  DCD [Digital Core Design]
Direct Link  http://www.digitalcoredesign.com
Logo DCD - Digital Core Design

D16750 Datasheet(HTML) 3 Page - Digital Core Design

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All trademarks mentioned in this document
are trademarks of their respective owners.
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.
http://www.DigitalCoreDesign.com
http://www.dcd.pl
DELIVERABLES
Source code:
VHDL Source Code or/and
VERILOG Source Code or/and
Encrypted, or plain text EDIF netlist
VHDL & VERILOG test bench
environment
Active-HDL automatic simulation macros
ModelSim automatic simulation macros
Tests with reference responses
Technical documentation
Installation notes
HDL core specification
Datasheet
Synthesis scripts
Example application
Technical support
IP Core implementation support
3 months maintenance
Delivery the IP Core updates, minor
and major versions changes
Delivery the documentation updates
Phone & email support
CONFIGURATION
The following parameters of the D16750 core
can be easy adjusted to requirements of
dedicated
application
and
technology.
Configuration of the core can be prepared by
effortless changing appropriate constants in
package file. There is no need to change any
parts of the code.
- enable
Baud generator
- disable
- enable
External RCLK source
- disable
- enable
External BAUDCLK source
- disable
- enable
Modem Control logic
- disable
- enable
SCR Register
- disable
- enable
FIFO Control logic
- disable
- standard 16/64
FIFO size
- large up to 512
DESIGN FEATURES
The functionality of the D16750 core was
based on the Texas Instruments TL16C750A.
The following characteristics differentiate the
D16750 from Texas Instruments devices:
The bi-directional data bus has been split
into
two
separate
buses:
datai(7:0),
datao(7:0)
Signals rd2 and wr2, xin, and xout have
been removed from interface
Signal ADS and address latch have been
removed
The DLL, DLM and THR registers are
reset to all zeros
TEMT and THRE bits of Line Status
Register, are reset during the second
clock rising edge following a THR write
RCLK clock is replaced by global clock
CLK, internally divided by BAUD factor.
Asynchronous microcontroller interface is
replaced by equivalent Universal interface
All latches implemented in original 16750
devices are replaced by equivalent flip-flop
registers, with the same functionality


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