512K x 8 Static RAM
fax id: 1079
CY62148
PRELIMINARY
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
December 1996 - Revised July 31, 1997
1CY 621 48
Features
• 4.5V
−5.5V operation
• CMOS for optimum speed/power
• Low active power
— 660 mW (max.)
• Low standby power (L version)
— 2.75 mW (max.)
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE options
Functional Description
The CY62148 is a high-performance CMOS static RAM orga-
nized as 524,288 words by 8 bits. Easy memory expansion is
provided by an active LOW chip enable (CE), an active LOW
output enable (OE), and three-state drivers. This device has
an automatic power-down feature that reduces power con-
sumption by more than 99% when deselected.
Writing to the device is accomplished by taking chip enable
one (CE) and write enable (WE) inputs LOW. Data on the eight
I/O pins (I/O0 through I/O7) is then written into the location
specified on the address pins (A0 through A18).
Reading from the device is accomplished by taking chip en-
able one (CE) and output enable (OE) LOW while forcing write
enable (WE). Under these conditions, the contents of the
memory location specified by the address pins will appear on
the I/O pins.
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
The CY62148 is available in a standard 450-mil-wide body
width SOIC package.
Selection Guide
CY62148–55
CY62148–70
Maximum Access Time (ns)
55
70
Maximum Operating Current
Commercial
120 mA
120 mA
Maximum CMOS Standby Current
Commercial
2 mA
2 mA
L
0.5 mA
0.5 mA
Shaded areas contain advance information
Logic Block Diagram
A1
A2
A3
A4
A5
A6
A7
A8
COLUMN
DECODER
INPUT BUFFER
POWER
DOWN
WE
OE
I/O0
I/O1
I/O2
I/O3
512K x 8
I/O7
I/O6
I/O5
I/O4
A0
A
10
CE
A9
62148-1
1
2
3
4
5
6
7
8
9
10
11
14
19
20
24
23
22
21
25
28
27
26
Top View
12
13
29
32
31
30
16
15
17
18
GND
A16
A14
A12
A7
A6
A5
A4
A3
WE
VCC
A15
A13
A8
A9
I/O7
I/O6
I/O5
I/O4
A2
I/O0
I/O1
I/O2
CE
OE
A10
I/O3
A1
A0
A11
A17
A18
SOIC
ARRAY
Pin Configuration
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