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TMP92CD54I Datasheet(PDF) 27 Page - Toshiba Semiconductor |
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TMP92CD54I Datasheet(HTML) 27 Page - Toshiba Semiconductor |
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27 / 343 page  2006-01-27 92CD54I-27 TMP92CD54I Since a transfer counter is a 16-bit counter, up to 65536 micro DMA processing operations can be performed per interrupt source (provided that the transfer counter for the source is initially set to 0000H). Micro DMA processing can be initiated by any one of 43 different interrupts – the 42 interrupts shown in the micro DMA start vectors in Table 3.4.1 and a micro DMA soft start. Figure 3.4.2 shows a 2-byte transfer carried out using a micro DMA cycle in Transfer Destination Address INC Mode (micro DMA transfers are the same in every mode except Counter Mode). (The conditions for this cycle are as follows: external 8-bit bus, 0 waits, and even-numbered transfer source and transfer destination addresses). src One state CLK A0 ∼23 1 2 3 4 5 dst Figure 3.4.2 Timing for micro DMA cycle States 1, 2 : Instruction fefetch cycle (pretches the next instruction code) State 3 : Micro DMA read cycle State 4 : Micro DMA write cycle State 5: (The same as in state 1, 2) (2) Micro DMA operation TMP92CD54I can initiate micro DMA either with an interrupt or by using the micro DMA soft start function, in which micro DMA is initiated by a Write cycle which writes to the register DMAR. Writing 1 to any bit of the register DMAR causes micro DMA to be performed once. On completion of the transfer, the bits of DMAR which support the end channel are automatically cleared to 0. When a burst is specified by the register DMAB, data is transferred continuously from the initiation of micro DMA until the value in the micro DMA transfer counter is 0. Symbol NAME Address 7 6 5 4 3 2 1 0 DREQ7 DREQ6 DREQ5 DREQ4 DREQ3 DREQ2 DREQ1 DREQ0 R/W DMAR DMA Request 109h (no RMW) 0 0 0 0 0 0 0 0 |
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