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TMP92CD54I Datasheet(PDF) 95 Page - Toshiba Semiconductor |
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TMP92CD54I Datasheet(HTML) 95 Page - Toshiba Semiconductor |
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95 / 343 page  2006-01-27 92CD54I-95 TMP92CD54I Setting example: To generate an INTT1 interrupt every 0.4 seconds at fc = 20 MHz, set the timer registers TREG0 and TREG1 as follows: If φT16 (6.4 µs at 20 MHz) is used as the input clock for counting, set the following value in the registers: 0.4 s ÷ 6.4 µs = 62500 = F424H; i.e. set TREG1 to F4H and TREG0 to 24H. The comparator match signal is output from timer 0 each time the up-counter UC0 matches TREG0, where the up-counter UC0 is not cleared. In the case of the timer 1 comparator, the match detect signal is output on each comparator pulse on which the values in the up-counter UC1 and TREG1 match. When the match detect signal is output simultaneously from both the comparators timer 0 and timer 1, the up-counters UC0 and UC1 are cleared to 0 and the interrupt INTT1 is generated. Also, if inversion is enabled, the value of the timer flip-flop TFF1 is inverted. Example: When TREG1 = 04H and TREG0 = 80H Figure 3.7.20 Timer output by 16-Bit Interval Timer Mode (3) 8-Bit Programmable Pulse Generation(PPG) Output Mode Square wave pulses can be generated at any frequency and duty ratio by timer 0. The output pulses may be active-Low or active-High. In this mode timer 1 cannot be used. Timer 0 outputs pulses on the TO1 pin (which can also be used as PC1). Figure 3.7.21 8 bit PPG output waveforms 0080H 0180H 0280H 0380H 0480H Value of up-counter(UC1, UC0): UC0 & TREG0 match detect signal 0000H Inversion Interrupt INTT1 Timer output TO1 UC1 & TREG1 match detect signal t tH tL TREG0 and UC0 match (Interrupt INTT0) TREG0 TREG1 TREG1 and UC0 match (Interruput INTT1) TO1 Duty cycle Period |
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