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TMP91FY28 Datasheet(PDF) 18 Page - Toshiba Semiconductor |
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TMP91FY28 Datasheet(HTML) 18 Page - Toshiba Semiconductor |
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18 / 60 page  TMP91FY28 2004-02-12 91FY28-16 Under development (7) Write operation status As shown in Table “Write status flags”, the flash memory provides several flag bits to determine the status of an embedded operation: DQ7, DQ6, DQ5 and DQ3. These status bits can be read during an embedded operation using the same timing as for read mode. The flash memory automatically returns to read mode when an embedded operation completes. The system can determine the operating status by referencing write status flags during an embedded operation. Once an embedded operation has completed, the system can determine the status by checking whether the data it has read matches the cell data. 1. DQ7 (Data polling) The data polling bit, DQ7, indicates to the host system the status of the embedded operation. Data polling is valid at the completion of the final bus cycle of a command sequence. When the embedded program algorithm is in progress, an attempt to read the flash memory will produce the complement of the data last written to DQ7. Upon completion of the embedded program algorithm, an attempt to read the flash memory will produce the true data last written to DQ7. Therefore, the system can use DQ7 to determine whether the embedded program algorithm is in progress or completed. When the embedded erase algorithm is in progress, an attempt to read the flash memory will produce a 0 at the DQ7 output. Upon completion of the embedded erase algorithm, the flash memory will produce a 1 at the DQ7 output. If there is a failure during an embedded operation, DQ7 continues to drive out the same value. The flash memory disables address latching when an embedded operation is complete. Data polling must be performed with a valid programmed address or an address within any of the non-protected blocks selected for erasure. 2. DQ6 (Toggle bit) The toggle bit, DQ6, also indicates to the host system the status of the embedded operation. Toggle bit is valid at the completion of the final bus cycle of a command sequence. Note that the erase operation will begin after the time-out has expired. When the embedded program algorithm is in progress, successive read cycles to any address cause DQ6 to toggle. If DQ6 is a 1 in the first read cycle, it will be a 0 in the next. Upon completion of the embedded program algorithm, DQ6 stops toggling and an attempt to read the flash memory will produce the data last written to DQ6. If there is a failure during an embedded operation, DQ6 still toggles. |
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