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TMP91CW28 Datasheet(PDF) 11 Page - Toshiba Semiconductor |
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TMP91CW28 Datasheet(HTML) 11 Page - Toshiba Semiconductor |
11 / 286 page TMP91CW28 2006-03-24 91CW28-9 3. Operation This section describes the functions and basic operation of each block constituting the TMP91CW28. See also section 7, “Points of Note and Restrictions” for an explanation of precautions and restrictions for individual blocks. 3.1 CPU The TMP91CW28 contains a high-performance 16-bit CPU called the 900/L1. For a detailed description of the CPU, refer to “TLCS-900/L1 CPU” in the preceding chapter. Functions unique to the TMP91CW28, which are not covered in “TLCS-900/L1 CPU”, are described below. 3.1.1 Reset Operation When resetting the TMP91CW28 microcontroller, ensure that the power supply voltage is within the operating voltage range, and that the internal high-frequency oscillator has stabilized. Then set the RESET input to low level at least for 10 system clocks (32 μs at 10 MHz). Thus, when turn on the switch, be set to the power supply voltage is within the operating voltage range, and that the internal high-frequency oscillator has stabilized. Then hold the RESET input to low level at least for 10 system clocks. Clock gear is initialized 1/16 mode by reset operation. It means that the system clock mode fSYS is set to fc/32 (= fc/16 × 1/2). The CPU performs the following operations as a result of a reset: • Set the program counter (PC) according to the reset vectors stored at addresses FFFF00H to FFFF02H PC [7:0] ← Value at FFFF00H PC [15:8] ← Value at FFFF01H PC [23:16] ← Value at FFFF02H • Set the stack pointer (XSP) to 100H. • Set the IFF2 to IFF0 bits of the status register (SR) to 111 (Setting the interrupt level mask register to level 7). • Set the MAX bit of the status register (SR) to 1 (Selecting maximum mode). • Clear the RFP2 to RFP0 bits of the status register (SR) to 000 (Selecting register bank0). After a reset, the CPU starts executing instructions according to the set PC. CPU internal registers other than the above are not modified. The on-chip I/O peripherals, ports and other pins are initialized as follows upon a reset. • All on-chip I/O peripheral registers are initialized. • All port pins, including those multiplexed with on-chip peripheral functions, are configured as either general-purpose inputs or general-purpose outputs. • The ALE pin is placed in high-impedance state. Note: A reset operation does not affect the contents of the on-chip RAM or the CPU registers other than PC, SR and XSP. Figure 3.1.1 shows TMP91CW28 reset timings. |
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