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TMP91CW28 Datasheet(PDF) 46 Page - Toshiba Semiconductor |
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TMP91CW28 Datasheet(HTML) 46 Page - Toshiba Semiconductor |
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46 / 286 page  TMP91CW28 2006-03-24 91CW28-44 (6) Precautions The CPU consists of a separate instruction execution unit and bus interface unit. It may fetch an instruction that clears the interrupt request flag for an interrupt (Note) immediately before that instruction is issued. Once the CPU accepts an interrupt, it may execute such an instruction before reading the interrupt vector. In such a case, the CPU reads 0008H (Interrupt vector cleared) and reads the interrupt vector from address FFFF08H. To prevent the above situation from arising, the DI instruction should be executed before an instruction for clearing an interrupt request flag. After the clear instruction is executed, at least one instruction should be executed before the EI instruction is executed to re-enable interrupts. If the EI instruction immediately follows the clear instruction, interrupts may be enabled before the interrupt flag is cleared. When the POP SR instruction is used to modify the interrupt mask level (SR.IFF[2:0]), the DI instruction must be executed to disable interrupts before executing the POP SR instruction. Also note the following two exceptional circuits: When INT0 is used as a level-sensitive interrupt pin, rather than edge-triggered, the interrupt request flip-flop is disabled so that a peripheral interrupt request directly passes through the S input of the flip-flop to appear at the S output. Modifying the mode (Edge to level) causes the previous interrupt request flag to be cleared automatically. INT0 level detection mode If INT0 is driven from low to high, causing the CPU to start an interrupt response sequence, INT0 must be held high until the interrupt response sequence is completed. When INT0 in level-sensitive mode is used to exit a HALT mode, INT0 must also be held high once it is driven from low to high. Ensure that it is not temporarily driven low due to noise during that period. When the INT0 detection mode is changed from level to edge, any interrupt request flag accepted in level-sensitive mode is not cleared. Use the following sequence to clear the interrupt request flag: DI LD (IIMC), 00H ; Change from level to edge. LD (INTCLR), 0AH ; Clear INT0 interrupt request flag. NOP ; Wait EI instruction. EI INTRXn Clearing the interrupt request flip-flop requires a system reset or reading the serial channel receive buffer. It cannot be cleared by writing INTCLR register. Note: The following instructions and pin state transition are also equivalent to this type of instruction: INT0: Instruction that changes the pin mode to level detection after an interrupt occurs in edge-triggered mode. Change in the pin input (from high to low) after an interrupt occurs level-sensitive mode. INTRXn: Instruction that reads the receive buffer. |
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