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TMP91C025FG Datasheet(PDF) 25 Page - Toshiba Semiconductor |
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TMP91C025FG Datasheet(HTML) 25 Page - Toshiba Semiconductor |
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25 / 260 page  TMP91C025 2007-02-28 91C025-23 3.3.4 Prescaler Clock Controller For the internal I/O (TMRA01 to TMRA23, SIO0 to SIO1) there is a prescaler which can divide the clock. The φT0 clock input to the prescaler is either the clock fFPH divided by 4 or the clock fc/16 divided by 4. The setting of the SYSCR0<PRCK0:1> register determines which clock signal is input. 3.3.5 Clock Doubler (DFM) DFM outputs the fDFM clock signal, which is four times as fast as fOSCH. It can use the low-frequency oscillator, even though the internal clock is high frequency . A reset initializes DFM to stop status, setting to DFMCR0-register is needed before use. Like an oscillator, this circuit requires time to stabilize. This is called the lock up time. The following example shows how DFM is used. DFMCR0 EQU 00E8H DFMCR1 EQU 00E9H LD (DFMCR1), 00001011B DFM parameter setting. LD (DFMCR0), 01X0XXXXB ; Set lock up time to 2 12/4 MHz. Enables DFM operation and starts lock up. LUP: BIT 5, (DFMCR0) ; JR NZ, LUP ; Detects end of lock up. LD (DFMCR0), 10X0XXXXB ; Changes fc from 4 MHz to 16 MHz. (Changes fSYS from 2 MHz to 8 MHz.) X: Don't care Note: Input frequency limitation and correction for DFM Recommend to use Input frequency (High-speed oscillation) for DFM in the following condition. • fOSCH = 4 to 9 MHz (Vcc = 3.0 to 3.6 V): Write 0BH to DFMCR1 • fOSCH = 4 to 6.75 MHz (Vcc = 2.7 to 3.6 V): Write 0BH to DFMCR1 10 01 Counts up by fOSCH During lock up <ACT1:0> DFM output: fDFM Lock up timer <DLUPFG> System clock fSYS Starts DFM operation. Starts lock up. Ends of lock up. Changes from 4 MHz to 16 MHz. After lock up |
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Similar Description - TMP91C025FG |
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