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TMP91C025FG Datasheet(PDF) 6 Page - Toshiba Semiconductor |
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TMP91C025FG Datasheet(HTML) 6 Page - Toshiba Semiconductor |
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6 / 260 page  TMP91C025 2007-02-28 91C025-4 Figure 1.1 TMP91C025 Block Diagram ( ): Initial function after reset AN2/MX (P82) AN3/MY/ ADTRG (P83) AN0, AN1 (P80, P81) AVCC, AVSS VREFH, VREFL 10-bit 4-channel AD converter TXD0 (PC0) RXD0 (PC1) SCLK0/ 0 CTS (PC2) SIO/UART/IrDA (SIO0) TXD1 (PC3) RXD1 (PC4) SCLK1/ 1 CTS (PC5) SIO/UART (SIO1) PX/INT2 (PB5) PY/INT3 (PB6) Touch screen I/F (TSI) 8-bit timer (TMRA0) TA0IN/INT1 (PB4) 8-bit timer (TMRA1) TA1OUT/KO1 (PA1) 8-bit timer (TMRA2) 8-bit timer (TMRA3) TA3OUT/KO2 (PA2) Port 6 Port 8 Port 9 Port A Port B Port C Port D LCD controller D1BSCP (PD0) D2BLP (PD1) D3BFR (PD2) DLEBCD (PD3) DOFFB (PD4) W A B C D E H L IX IY IZ SP XWA XBC XDE XHL XIX XIY XIZ XSP 32 bits F PC CPU (TLCS-900/L1) WDT (Watchdog timer) H-OSC X1 Clock gear, Clock doubler L-OSC DVSS [2] DVCC [2] X2 EMU0 EMU1 XT1 XT2 AM1 AM0 RESET D0 to D7 A0 to A7 A8 to A15 Port 1 P10 to P17 (D8 to D15) Port 2 P20 to P27 (A16 to A23) Port 5 Port Z RD WR HWR (PZ2) WAIT (P56) CS/WAIT controller (4 blocks) 0 CS to 3 CS , A 2 CS (P60 to P63) MMU Interrupt controller Keyboard I/F Melody/ alarm out RTC EA24/ B 2 CS / SRLB (P64) EA25/ C 2 CS / SRUB (P65) INT0 ( PS ) INT0 to INT3 (PB3 to PB6) KI0 to KI7 (P90 to P97) KO0/ ALARM / MLDALM (PA0) KO1/TA1OUT (PA1) KO2/TA3OUT (PA2) KO3 (PA3) MLDALM (PD7) ALARM / MLDALM /KO0 (PA0) R/ W / SRWR (PZ3) SR |
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Similar Description - TMP91C025FG |
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