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TMPR4951B Datasheet(PDF) 76 Page - Toshiba Semiconductor

Part # TMPR4951B
Description  64-Bit TX System RISC TX49 Family
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Manufacturer  TOSHIBA [Toshiba Semiconductor]
Direct Link  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

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Chapter 3 TX49/L3 Core’s Registers
3-22
3.2.17 XContext Register (Reg
#20)
The XContext register is a read/write register, and contains a pointer to an entry in the page table
entry (PTE) array, an operating system data structure that stores virtual to physical address translations.
When there is a TLB miss, the operating system software loads the TLB with the missing translation
from the PTE array.
However the contents of this register duplicates some information of the
BadVAddr register, it is arranged in a form that is more useful for TLB exception handler by a software.
This register is for use with the XTLB refill handler, which loads TLB entries for references to a 64-bit
address space, and is included solely for operating system use. The operating system sets the PTE base
field in the register, as needed. Normally, the operating system uses this register to address the current
page map which resides in the Kernel mapped segment, kseg3.
The BadVPN2 field of 27 bits has bits 39-13 of the virtual address that caused the TLB miss; bit 12 is
excluded because a single TLB entry maps to an even-odd page pair. For a 4-KByte page size, this
format may be used directly to access the pair-table of 8-Byte PTEs. For other page sizes and PTE
sizes, shifting and masking this value produces the appropriate address.
Figure 3.2.17 shows the format of the XContext register and Table 3.2.18 describes the XContext
register field.
63
33 32 31 30
4 3
0
PTEBase
R
BadVPN2
0
Figure 3.2.17 XContext Register Format
Table 3.2.18 XContext Register Field Description
Bit
Field
Description
Cold Reset
Read/Write
63:33
PTEBase
Page table entry base pointer
This field is normally written with a value that allows the
operation system to use the Context register as a pointer
into the current PTE array in memory.
Undefined
Read/Write
32:31
R
The Region field contains bits 63 to 62 of the virtual address.
00: user, 01: supervisor, 11: kernel
Undefined
Read/Write
30:4
BadVPN2
Bad virtual page number divided by two.
This field is written by hardware on a miss. It contains the
VPN of the most recent invalidly translated virtual address.
Undefined
Read
3:0
0
Reserved
0x0
Read


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