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TMPR3927 Datasheet(PDF) 50 Page - Toshiba Semiconductor |
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TMPR3927 Datasheet(HTML) 50 Page - Toshiba Semiconductor |
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50 / 512 page  Chapter 3 Pins 3-4 Signal Name I/O Description Interrupt signals NMI* I Non Maskable Interrupt Non-maskable interrupt signal. The pin is equipped with an internal pull-up resistor. INT [5:4] I Interrupt Request External interrupt request signals. INT[5] and INT[4] are multiplexed with CTS0 and RTS0, respectively. The pins are equipped with internal pull-up resistors. INT [3:0] I Interrupt Request External interrupt request signals. The pins are equipped with internal pull-up resistors. Timer interface TIMER [1:0] O Timer Pulse Width Output Timer output signals used in pulse generator mode. The pins output “1” in other modes. The pins are multiplexed with other functions. DMAREQ[3]/PIO[15]/TIMER[1] DMAACK[3]/PIO[11]/TIMER[0] DMADONE*/PIO[7]/TIMER[0] TCLK I External Timer Clock Timer input clock signal. TMR0, TMR1, and TMR2 share this signal. The pin is multiplexed with PIO[13] and DMAREQ[2]. Memory interface SDCLK [4:0] O SDRAM Clock Out Outputs one half the frequency of the TX39/H2 core (e.g., 66 MHz when the TX39/H2 is operating at 133 MHz), which is used as a clock for SDRAM and SMROM, as well as for I/O devices that run in full speed bus mode. Only SDCLK[0] is equipped with an internal pull-up resistor. SDCLK[0] must be enabled when an SDRAM is used. RAS* O Row Address Strobe RAS* signal for SDRAM, SMROM, and SGRAM. CAS* O Column Address Strobe CAS* signal for SDRAM, SMROM, and SGRAM. SDCS [7:0] * O Synchronous Memory Device Chip Select Chip select signals for SDRAM, SMROM, SGRAM, and 100-pin DIMM flash memory. The SDCS[7:2] pins are multiplexed with CE[7:2]. SDCS[7:6] are also multiplexed with DMAREQ[1]/PIO[11] and DMAACK[1]/PIO[10]. The SDCS[7:6] pins are equipped with internal pull-up resistors. DQM [3:0] * O Data Mask During a write cycle, the DQM signals function as a data mask and can control individual bytes of the input data for SDRAM. During a read cycle, they control the SDRAM output buffers. The DQM signals also function as byte enable signals for DIMM flash memory during a write cycle. WE* O Write Enable WE* signal for SDRAM, SMROM, and SGRAM. CKE O Clock Enable CKE signal for SDRAM, SMROM, and SGRAM. SWE* O SRAM Write Enable Write enable signal for SRAM and I/O devices. |
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Similar Description - TMPR3927 |
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