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TMP1942FDU Datasheet(PDF) 3 Page - Toshiba Semiconductor |
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TMP1942FDU Datasheet(HTML) 3 Page - Toshiba Semiconductor |
3 / 106 page TMP1942FD TMP1942FD-2 (1) TX19 core processor 1) Two instruction set architecture (ISA) modes: 16-bit ISA for code efficiency and 32-bit ISA for performance. • The 16-bit ISA is object-code compatible with the code-efficient MIPS16TM ASE. • The 32-bit ISA is object-code compatible with the high-performance TX39 family. 2) High performance combined with low power consumption - High performance • Single clock cycle execution for most instructions • 3-operand arithmetic instructions for high instruction throughput • 5-stage pipeline • On-chip high-speed memory • DSP function: Executes 32-bit x 32-bit multiply operations in a single clock cycle. - Low power consumption • Optimized design using a low-power cell library • Programmable standby modes in which processor clocks are stopped 3) Fast interrupt response suitable for real-time control • Distinct starting locations for each interrupt service routine • Automatically generated vectors for each interrupt source • Automatic updates of the interrupt mask level ( 2) On-chip RAM: TMP1942FDU/FDXB 20 KB On-chip FROM TMP1942FDU/FDXB 512 KB ROM correction function (8 words x 4 blocks) ( In the flash-version product, only the registers exist and no correction is performed.) ( 3) External memory expansion • 16-Mbyte off-chip address space for code and data • External bus interface with dynamic bus sizing for 8-bit and 16-bit data ports ( 4) 4-channel DMA controller • Interrupt- or software-triggered ( 5) 6-channel 8-bit PWM timer • 12-channel 8-bit interval timer • 6-channel 16-bit interval timer • 6-channel 8-bit PPG output ( 6) 14-channel 16-bit timer • Two channels support two-phase input pulse counter mode. ( 7) 1-channel RTC timer ( 8) 5-channel general-purpose serial interface • Supports both UART and synchronous transfer modes. |
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