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SN74V3640 Datasheet(PDF) 15 Page - Texas Instruments

Part # SN74V3640
Description  102436, 204836, 409636, 819236, 1638436, 32768 횞 36 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

SN74V3640 Datasheet(HTML) 15 Page - Texas Instruments

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SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690
1024
× 36, 2048 × 36, 4096 × 36, 8192 × 36, 16384 × 36, 32768 × 36
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS668A – NOVEMBER 2001 – REVISED MARCH 2003
15
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see Figure 2 through Figure 22)
SN74V3640-6
SN74V3650-6
SN74V3660-6
SN74V3670-6
SN74V3680-6
SN74V3690-6
SN74V3640-7
SN74V3650-7
SN74V3660-7
SN74V3670-7
SN74V3680-7
SN74V3690-7
SN74V3640-10
SN74V3650-10
SN74V3660-10
SN74V3670-10
SN74V3680-10
SN74V3690-10
SN74V3640-15
SN74V3650-15
SN74V3660-15
SN74V3670-15
SN74V3680-15
SN74V3690-15
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
fclock
Clock cycle frequency
166
133.3
100
66.7
MHz
tA
Data access time
2
4.5
2
5
2
6.5
2
10
ns
tCLK
Clock cycle time
6
7.5
10
15
ns
tCLKH
Clock high time
2.5
3.5
4.5
6
ns
tCLKL
Clock low time
2.5
3.5
4.5
6
ns
tDS
Data setup time
1.5
2.5
3.5
4
ns
tDH
Data hold time
0.5
0.5
0.5
1
ns
tENS
Enable setup time
1.5
2.5
3.5
4
ns
tENH
Enable hold time
0.5
0.5
0.5
1
ns
tLDS
Load setup time
2
3.5
3.5
4
ns
tLDH
Load hold time
0
0.5
0.5
1
ns
tRS
Reset pulse duration‡
10
10
10
15
ns
tRSS
Reset setup time
15
15
15
15
ns
tRSR
Reset recovery time
10
10
10
15
ns
tRSF
Reset to flag and output time
15
15
15
15
ns
tRTS
Retransmit setup time
2
3.5
3.5
4
ns
tOLZ
Output enable to output in low impedance
0
0
0
0
ns
tOE
Output enable to output valid
2
4.5
2
6
2
6
2
8
ns
tOHZ
Output enable to output in high impedance
2
4.5
2
6
2
6
2
8
ns
tWFF
Write clock to FF or IR
4.5
5
6.5
10
ns
tREF
Read clock to EF or OR
4.5
5
6.5
10
ns
tPAFA
Clock to asynchronous PAF
8.5
12.5
16
20
ns
tPAFS
Write clock to synchronous PAF
4.5
5
6.5
10
ns
tPAEA
Clock to asynchronous PAE
8.5
12.5
16
20
ns
tPAES
Read clock to synchronous PAE
4.5
5
6.5
10
ns
tHF
Clock to HF
9
12.5
16
20
ns
tsk1
Skew time between read clock and
write clock for EF/OR and FF/IR
4.5
5
7
9
ns
tsk2
Skew time between read clock and
write clock for PAE and PAF
4.5
7
10
14
ns
† All ac timings apply to standard mode and FWFT mode.
‡ Pulse durations less than minimum values are not allowed.


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