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ISL9216 Datasheet(PDF) 25 Page - Intersil Corporation |
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ISL9216 Datasheet(HTML) 25 Page - Intersil Corporation |
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25 / 33 page  25 FN6488.1 November 2, 2007 DEFINITION OF CELL BALANCING Cell balancing is defined as the application of differential currents to individual cells (or combinations of cells) in a series string. Normally, of course, cells in a series string receive identical currents. A battery pack requires additional components and circuitry to achieve cell balancing. For the ISL9216 and ISL9217 devices, the only external components required are balancing resistors. CELL BALANCE OPERATION Cell balancing is accomplished through a microcontroller algorithm. This algorithm compares the cell voltages (a representation of the pack capacity) and turns on balancing for the cells that have the higher voltages. There are many parameters that should be considered when writing this algorithm. An example cell balancing algorithm is available in the ISL9216EVAL1Z evaluation kit. The microcontroller turns on the specific cell balancing by setting a bit in the Cell Balance Register. Each bit in the register corresponds to one cell’s balancing control. When the bit is set, an internal cell balancing FET turns on. This shorts an external resistor across the specified cell. The maximum current that can be drawn from (or bypassed around) the cell is 200mA. This current is set by selecting the value of the external resistor. Figure 7 shows an example with a 200mA (maximum) balancing current. With lower balancing current, more balancing FETs can be turned on at once, without exceeding the device power dissipation limits or generating excessive balancing current that will heat the external resistor. External VMON/CFET Protection Mechanisms When there is a single charge/discharge path, a blocking diode is required in the ISL9216 VMON to P- path. See D1 in Figure 8. This diode is to protect against a negative voltage on the VMON pin that can occur when the FETs are off and the charger connects to the pack. This diode is not needed when there is a separate charge and discharge path, because the voltages on P- (discharge) are likely always positive. For the cascaded combination of ISL9216 and ISL9217, a zener diode (D2 in Figure 8) needs to be in the ISL9216 VMON path to the P- pin to protect the ISL9216 from an overvoltage condition when the FETs open due to a short circuit or overcurrent condition. With the single set of charge/discharge FETs, the ISL9216 CFET pin needs to be protected in the event of an over- current or short circuit shut-down. When this happens, the FET opens suddenly. The flyback voltage from the motor windings will likely exceed the maximum input voltage on the CFET pin. So, when operating in this configuration, an additional external series diode must be placed between the CFET pin of the ISL9216 and the gate of the Charge FET. See Diode D3 in Figure 8. This will reduce the CFET gate voltage, but not significantly. Finally, in all configurations, to protect the Charge FET itself in the event of a large negative voltage on the Pack- pin, zener diode D4 is added. The large negative voltage can occur when the P- pin goes significantly negative, while the CFET pin is being internally clamped at VSS. The zener voltage of D4 should be less than the VGS(max) specification of the FET. CELL ISL9216, ISL9217 BALANCE REG VC7/VCC VSS FIGURE 7. CELL BALANCING CONTROL EXAMPLE WITH 100mA BALANCING CURRENT 7 654 321 21 Ω 200mA 1W 21 Ω 1W VCELL1 CB1 CB7 MUST ASSUME ZERO rDS(ON) FOR MAX CURRENT CALCULATION PACK- PACK+ ISL9216 ISL9217 CFET DFET D3 D4 D2 D1 1M VMON FIGURE 8. USE OF A DIODES FOR PROTECTING THE CFET AND VMON PINS. 10M ISL9216, ISL9217 |
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Similar Description - ISL9216 |
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