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FN6488.1

November 2, 2007

Configuration Registers

The device is configured for specific application requirements using the Configuration Registers. The configuration register

consists of SRAM memory. This memory is powered by the RGO output. In a sleep condition, an internal switch powers the

contents of these registers from the VCELL1 input.

TABLE 7. DISCHARGE SET CONFIGURATION REGISTER (ADDR: 05H)

SETTING

FUNCTION

Bit 7

DENOCD

Turn off automatic OCD control

(ISL9216 only)

When set to ‘0’, a discharge overcurrent condition automatically turns off the FETs.

When set to ‘1’, a discharge overcurrent condition will not automatically turn off the FETs.

In either case, this condition sets the DOC bit, which also turns on the TEMP3V output.

Bit 6

OCDV1

Bit 5

OCDV0

Discharge Overcurrent Threshold

(ISL9216 only)

00

01

10

11

Bit 4

DENSCD

Turn off automatic SCD control

(ISL9216 only)

When set to ‘0’, a discharge short circuit condition turns off the FETs.

When set to ‘1’, a discharge short circuit condition will not automatically turn off the FETs.

In either case, the condition sets the SCD bit, which also turns on the TEMP3V output.

Bit 3

SCDV1

Bit 2

SCDV0

Discharge Short Circuit Threshold

(ISL9216 only)

00

01

10

11

Bit 1

OCDT1

Bit 0

OCDT0

Discharge Overcurrent Time-out

(ISL9216 only)

00

01

10

11

ISL9216, ISL9217