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MC9S08SH8 Datasheet(PDF) 60 Page - Freescale Semiconductor, Inc |
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MC9S08SH8 Datasheet(HTML) 60 Page - Freescale Semiconductor, Inc |
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60 / 330 page  Chapter 5 Resets, Interrupts, and General System Control MC9S08SH8 MCU Series Data Sheet, Rev. 1 60 Freescale Semiconductor 5.4 Computer Operating Properly (COP) Watchdog The COP watchdog is intended to force a system reset when the application software fails to execute as expected. To prevent a system reset from the COP timer (when it is enabled), application software must reset the COP counter periodically. If the application program gets lost and fails to reset the COP counter before it times out, a system reset is generated to force the system back to a known starting point. After any reset, the COP watchdog is enabled (see Section 5.7.4, “System Options Register 1 (SOPT1),” for additional information). If the COP watchdog is not used in an application, it can be disabled by clearing COPT bits in SOPT1. The COP counter is reset by writing 0x0055 and 0x00AA (in this order) to the address of SRS during the selected timeout period. Writes do not affect the data in the read-only SRS. As soon as the write sequence is done, the COP timeout period is restarted. If the program fails to do this during the time-out period, the MCU will reset. Also, if any value other than 0x0055 or 0x00AA is written to SRS, the MCU is immediately reset. The COPCLKS bit in SOPT2 (see Section 5.7.5, “System Options Register 2 (SOPT2),” for additional information) selects the clock source used for the COP timer. The clock source options are either the bus clock or an internal 1-kHz clock source. With each clock source, there are three associated time-outs controlled by the COPT bits in SOPT1. Table 5-1 summaries the control functions of the COPCLKS and COPT bits. The COP watchdog defaults to operation from the 1-kHz clock source and the longest time-out (210 cycles). Table 5-1. COP Configuration Options When the bus clock source is selected, windowed COP operation is available by setting COPW in the SOPT2 register. In this mode, writes to the SRS register to clear the COP timer must occur in the last 25% of the selected timeout period. A premature write immediately resets the MCU. When the 1-kHz clock source is selected, windowed COP operation is not available. Control Bits Clock Source COP Window1 Opens (COPW = 1) 1 Windowed COP operation requires the user to clear the COP timer in the last 25% of the selected timeout period. This column displays the minimun number of clock counts required before the COP timer can be reset hen in windowed COP mode (COPW = 1). COP Overflow Count COPCLKS COPT[1:0] N/A 0:0 N/A N/A COP is disabled 0 0:1 1 kHz N/A 25 cycles (32 ms2) 2 Values shown in in miliseconds based on t LPO = 1 ms. See tLPO in the appendix Section A.12.1, “Control Timing” for the tolerance of this value. 0 1:0 1 kHz N/A 28 cycles (256 ms1) 0 1:1 1 kHz N/A 210 cycles (1.024 s1) 1 0:1 Bus 6144 cycles 213 cycles 1 1:0 Bus 49,152 cycles 216 cycles 1 1:1 Bus 196,608 cycles 218 cycles |
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