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W682388 Datasheet(PDF) 2 Page - Winbond |
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W682388 Datasheet(HTML) 2 Page - Winbond |
2 / 8 page W682388 Layout Guideline Rev 1.3 Idle Channel Noise (ICN) performance can be further improved by splitting the 3.3V power plane. This way the front end power (VDD1 – VDD4) and ground (GND1 – GND4 & VSSP) will be isolated from the main 3.3V and Ground planes by using ferrite beads. 2. DC-TO-DC Converter Layout The W682388 DC-to-DC converter circuit uses pulse width modulation to generate the desired voltages. Lay out this circuit carefully to minimize the contributed noise from the high switching currents. The DC-to-DC converter has specific areas to optimize to minimize this noise effect. The critical areas are described below: Loop 1 in Figure 1 is the secondary fly-back current path that generates the negative VBAT potential. Place the components in this area in a tight loop. Cover the open areas in between with as much copper as possible. Loop 2 in Figure 1 is the primary input current loop for the DC-to-DC converter from the unregulated power supply. Place the capacitors in this area near the sense resistor to maximize results. Voltage Sense Resistors (Rdh and Rdl) 100V DCP1 C34 0.1UF 100V Loop 2 R45 200 Single point connection to Ground Current Sense Resistor (Ris) BAT1 D4 ES1D R41 (Rdh) 56.2K DCH1 R42 (Rdl) 56.2K DC_UNREG Loop 1 C36 0.1UF C31 10UF Q16 ZX5T955G 1 DC_IN_CH1 R39 (Re1) 200 BAT1 100V R38(Ris) 0.56 25V Q18 2N2222 2 DCN1 L 150UH DCL1 C29 10UF Figure 1. DC-to-DC Converter Circuit AN-CS006a_W682388 PCB Layout.doc Page 2 of 8 |
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