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ES6425FF Datasheet(PDF) 3 Page - ESS Technology,Inc

Part # ES6425FF
Description  Digital Media Processor 2 Product Brief
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Manufacturer  ESS [ESS Technology,Inc]
Direct Link  http://www.esstech.com
Logo ESS - ESS Technology,Inc

ES6425FF Datasheet(HTML) 3 Page - ESS Technology,Inc

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ESS Technology, Inc.
SAM0529-091305
3
ES6425 PRODUCT BRIEF
ES6425 PIN DESCRIPTION
ES6425 PIN DESCRIPTION
Table 1 lists the pin descriptions for the ES6425. The
pound symbol (#) denotes an active-low signal.
Table 1
ES6425 Pin Description
Name
Pin Numbers
I/O
Definition
VEE
1,18, 27, 59, 68, 75,
92, 99, 104, 130,
148, 157, 159, 164,
183, 193, 201
P
I/O power supply.
LA[21:0]
2-7, 10-16, 19-23,
204-207
O
RISC port address bus.
VSS
8, 17, 26, 34, 43,
60, 67, 76, 84, 91,
98, 103, 120, 129,
138, 147, 156, 163,
171, 177, 184, 192,
200, 208
G
Ground.
VCC
9, 35, 44, 83, 121,
139, 172
I
Core power supply.
RESET#
24
I
Reset input (active-low); (5V tolerant input).
TDMDX
25
O
TDM transmit data.
RSEL
I
LCS3 ROM Boot Data Width Select. Strapped to VCC or ground via 4.7-k
resistor; read during reset.
TDMDR
28
I
TDM receive data; (5V tolerant input).
TDMCLK
29
I
TDM clock; (5V tolerant input).
TDMFS
30
I
TDM frame sync; (5V tolerant input).
TDMTSC#
31
O
TDM output enable (active-low).
TWS
32
O
Audio transmit frame sync.
SEL_PLL2
I
System and DSCK output clock frequency selection is made at the rising edge of
RESET#. The matrix below lists the available clock frequencies and their
respective PLL bit settings. Pull up to VCC via 4.7-k
Ω resistor for proper
operation; read during reset.
TSD0
33
O
Audio transmit serial data output 0.
SEL_PLL0
I
Pull up to VCC via 4.7-k
Ω resistor for proper operation; read during reset.
RSEL
Selection
016-bit ROM
18-bit ROM
SEL_PLL2
SEL_PLL1
SEL_PLL0
Clock Type
0
0
0
DCLK x 4.5
0
0
1
DCLK x 5.0
0
1
0
Bypass mode
0
1
1
DCLK x 4.0
1
0
0
DCLK x 4.25
1
0
1
DCLK x 4.75
1
1
0
DCLK x 5.5
1
1
1
DCLK x 6.0


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