CXK77K36R320GB-3 datasheet(11/22 Pages) SONY

Part #	CXK77K36R320GB-3

Description	32Mb LW R-R HSTL High Speed Synchronous SRAM (1Mb x 36)

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Manufacturer	SONY [Sony Corporation]

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11 / 22 page

SONY®

CXK77K36R320GB

Preliminary

32Mb LW R-R, rev 0.6

11 / 22

March 16, 2004

Read-Write-Read Timing Diagram

Asynchronously Controlled via G and Dummy Read Operations (SS = Low)

Note: In the diagram above, two Dummy Read operations are inserted between Read and Write operations to control the data

bus transition from output to input. This depiction is for clarity purposes only. It is NOT a requirement. Depending on the ap-

plication, one Dummy Read operation may be sufficient.

A4

A6

A7

SA

SW

G

DQ

Q1

D5

D6

Q2

Q3

D4

A1

Q7

Read

Write

Read

Figure 3

K

A2

A5

SS = VIL

tKHQX

tKHQZ

tKHQX1

tKHQV

SBWx

A3

tGLQX

tGLQV

tGHQZ

Dummy

A8

A9

tKHDX

tDVKH

tKHWX

tWVKH

tKHAX

tAVKH

tKHWX

tWVKH

tKHKH

tKLKH

tKHKL

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