K7S3236T4C

K7S3218T4C

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Rev. 1.2 March 2007

Programmable Impedance Output Buffer Operation

Output Valid Pin (QVLD)

Depth Expansion

The Q Valid indicates valid output data. QVLD is activated half cycle before the read data for the receiver to be ready for capturing

the data. QVLD is edge aligned with CQ and CQ.

Separate input and output ports enables easy depth expansion. Each port can be selected and deselected independently and read

and write operation do not affect each other. Before chip deselected, all read and write pending operations are completed.

The allowable range of RQ is between 175

desired. For example, 250

Impedance updates occur early in cycles that do not activate the outputs, such as deselect cycles. In all cases impedance updates

are transparent to the user and do not produce access time "push-outs" or other anomalous behavior in the SRAM. To guarantee

optimum output driver impedance after power up, the SRAM needs 1024 non-read cycles.

Power-Up/Power-Down Supply Voltage Sequencing

Echo clock operation

To assure the output traceability, the SRAM provides the output Echo clock, pair of compliment clock CQ and CQ, which are syn-

chronized with internal data output. Echo clocks run free during normal operation.

The Echo clock is triggered by internal output clock signal, and transferred to external through same structures as output driver.