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S29GL032N11FFIV23 Datasheet(PDF) 73 Page - SPANSION |
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S29GL032N11FFIV23 Datasheet(HTML) 73 Page - SPANSION |
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73 / 79 page  November 16, 2007 S29GL-N_01_09 S29GL-N MirrorBit® Flash Family 73 Data She e t 16. Erase And Programming Performance Notes 1. Typical program and erase times assume the following conditions: 25 °C, VCC = 3.0V, 10,000 cycles; checkerboard data pattern. 2. Under worst case conditions of 90 °C; Worst case V CC, 100,000 cycles. 3. Programming time (typ) is 15 μs (per word), 7.5 μs (per byte). 4. Accelerated programming time (typ) is 12.5 μs (per word), 6.3 μs (per byte). 5. Write buffer Programming time is calculated on a per-word/per-byte basis for a 16-word/32-byte write buffer operation. 6. In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure. 7. System-level overhead is the time required to execute the command sequence(s) for the program command. See Table 10.1 on page 51 and Table 10.3 on page 53 for further information on command definitions. Notes 1. Sampled, not 100% tested. 2. Test conditions TA = 25°C, f = 1.0 MHz. Parameter Typ (Note 1) Max (Note 2) Unit Comments Sector Erase Time 0.5 3.5 sec Excludes 00h programming prior to erasure (Note 6) Chip Erase Time S29GL032N 32 64 S29GL064N 64 128 Total Write Buffer Program Time (Notes 3, 5) 240 µs Excludes system level overhead (Note 7) Total Accelerated Effective Write Buffer Program Time (Notes 4, 5) 200 Chip Program Time S29GL032N 31.5 sec S29GL064N 63 Table 16.1 TSOP Pin and BGA Package Capacitance Parameter Symbol Parameter Description Test Setup Typ Max Unit CIN Input Capacitance VIN = 0 TSOP 6 10 pF BGA TBD TBD pF COUT Output Capacitance VOUT = 0 TSOP 6 12 pF BGA TBD TBD pF CIN2 Control Pin Capacitance VIN = 0 TSOP 6 10 pF BGA TBD TBD pF CIN3 #RESET, #WP/ACC Pin Capacitance VIN = 0 TSOP 27 30 pF BGA TBD TBD pF |
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