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74LVC2G02 Datasheet(PDF) 3 Page - NXP Semiconductors |
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74LVC2G02 Datasheet(HTML) 3 Page - NXP Semiconductors |
3 / 15 page 74LVC2G02_5 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 05 — 4 September 2007 3 of 15 NXP Semiconductors 74LVC2G02 Dual 2-input NOR gate 6. Pinning information 6.1 Pinning 6.2 Pin description Fig 4. Pin configuration TSSOP8 and VSSOP8 74LVC2G02 1A VCC 1B 1Y 2Y 2B GND 2A 001aab642 1 2 3 4 6 5 8 7 Fig 5. Pin configuration XSON8 Fig 6. Pin configuration XQFN8 74LVC2G02 2B 1Y VCC 2A 2Y 1B 1A GND 001aab643 36 27 18 45 Transparent top view 001aae971 1B 2B 1A 2Y 1Y 2A Transparent top view 3 6 1 5 7 2 terminal 1 index area 74LVC2G02 Table 3. Pin description Symbol Pin Description TSSOP8, VSSOP8 XSON8 XQFN8 1A 1 1 7 data input 1B 2 2 6 data input 2Y 3 3 5 data output GND 444ground (0 V) 2A 5 5 3 data input 2B 6 6 2 data input 1Y 7 7 1 data output VCC 8 8 8 supply voltage |
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