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DS26556 Datasheet(PDF) 4 Page - Maxim Integrated Products |
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DS26556 Datasheet(HTML) 4 Page - Maxim Integrated Products |
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4 / 368 page  DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver 4 of 368 11.1.2 Global Status Registers ....................................................................................................................................107 11.2 CELL / PACKET REGISTER DESCRIPTIONS....................................................................................................113 11.2.1 General Cell / Packet Registers ........................................................................................................................114 11.2.2 Cell/Packet Status Registers.............................................................................................................................116 11.2.3 Transmit FIFO Registers...................................................................................................................................118 11.2.4 Transmit Cell Processor Registers....................................................................................................................123 11.2.5 Transmit Packet Processor Registers ...............................................................................................................130 11.2.6 Receive Cell Processor Registers.....................................................................................................................136 11.2.7 Receive Packet Processor Registers ................................................................................................................151 11.2.8 Receive FIFO Registers....................................................................................................................................163 11.3 SYSTEM INTERFACE REGISTERS..................................................................................................................166 11.3.1 Transmit System Interface Registers ................................................................................................................166 11.3.2 Receive System Interface Registers .................................................................................................................168 11.4 RECEIVE T1 FRAMER REGISTERS ...............................................................................................................171 11.4.1 Receive Master-Mode Register.........................................................................................................................174 11.4.2 Interrupt Information Register ...........................................................................................................................175 11.4.3 T1 Receive Control Registers ...........................................................................................................................176 11.4.4 T1 Line-Code Violation Count Register (LCVCR) .............................................................................................193 11.4.5 T1 Path-Code Violation Count Register (PCVCR) ............................................................................................194 11.4.6 T1 Frames Out-of-Sync Count Register (FOSCR) ............................................................................................195 11.4.7 DS0 Monitoring Function...................................................................................................................................196 11.4.8 Receive Signaling Registers .............................................................................................................................197 11.4.9 T1 Receive Per-Channel Idle Code Insertion ....................................................................................................200 11.4.10 T1 Receive Channel Mark Registers.................................................................................................................201 11.4.11 Receive Fractional T1 Support (Gapped-Clock Mode)......................................................................................202 11.4.12 Receive T1 Bit-Oriented Code (BOC) Controller...............................................................................................203 11.4.13 Receive SLC-96 Operation ...............................................................................................................................204 11.4.14 Receive FDL .....................................................................................................................................................205 11.4.15 Programmable In-Band Loop-Code Detection ..................................................................................................206 11.4.16 Receive HDLC Controller ..................................................................................................................................212 11.4.17 Receive BERT ..................................................................................................................................................218 11.5 T1 TRANSMIT FRAMER ................................................................................................................................220 11.5.1 Transmit-Master Mode Register........................................................................................................................223 11.5.2 Interrupt Information Registers..........................................................................................................................223 11.5.3 T1 Transmit Control Registers ..........................................................................................................................224 11.5.4 T1 Transmit Status and Information ..................................................................................................................229 11.5.5 T1 Per-Channel Loopback ................................................................................................................................232 11.5.6 T1 Transmit DS0 Monitoring Function...............................................................................................................233 11.5.7 T1 Transmit Signaling Operation.......................................................................................................................233 11.5.8 T1 Transmit Per-Channel Idle Code Insertion ...................................................................................................237 11.5.9 T1 Transmit Channel Mark Registers................................................................................................................238 11.5.10 Fractional T1 Support (Gapped Clock Mode)....................................................................................................239 11.5.11 T1 Transmit Bit Oriented Code (BOC) Controller ..............................................................................................240 11.5.12 T1 Transmit FDL ...............................................................................................................................................241 11.5.13 Transmit SLC–96 Operation .............................................................................................................................241 11.5.14 Transmit HDLC Controller .................................................................................................................................242 Transmit Interrupt Mask Register 2 .................................................................................................................................247 11.5.15 Programmable In-Band Loop-Code Generator .................................................................................................248 11.5.16 Interfacing the T1 Tx Formatter to the BERT ....................................................................................................250 11.5.17 T1 Transmit Synchronizer .................................................................................................................................252 11.6 E1 RECEIVE FRAMER .................................................................................................................................254 11.6.1 E1 Receive Framer Description and Operation.................................................................................................257 11.6.2 Receive Master Mode Register .........................................................................................................................257 11.6.3 Interrupt Information Registers..........................................................................................................................259 11.6.4 E1 Receive Control Registers ...........................................................................................................................259 11.6.5 E1 Receive Status and Information...................................................................................................................263 11.6.6 E1 Error Count Registers ..................................................................................................................................275 11.6.7 DS0 Monitoring Function...................................................................................................................................278 11.6.8 E1 Receive Signaling Operation .......................................................................................................................279 11.6.9 E1 Receive Per-Channel Idle Code Insertion....................................................................................................281 11.6.10 E1 Receive Channel Mark Registers ................................................................................................................282 11.6.11 Fractional E1 Support (Gapped Clock Mode) ...................................................................................................282 11.6.12 Additional Sa-Bit and Si-Bit Receive Operation (E1 Mode) ...............................................................................284 11.6.13 Receive Framer HDLC Controller .....................................................................................................................290 11.6.14 Interfacing the E1 Rx Framer to the BERT........................................................................................................297 |
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