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SM79108L25 Datasheet(PDF) 7 Page - SyncMOS Technologies,Inc |
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SM79108L25 Datasheet(HTML) 7 Page - SyncMOS Technologies,Inc |
7 / 25 page Specifications subject to change without notice,contact your sales representatives for the most recent information. 7/26 Ver 2.1 SM79108 08/2006 SyncMOS Technologies International. Inc. SM79108 Watch Dog Timer Registers - WDT Control Register (WDTC, 9FH) WDTE : Watch Dog Timer enable bit CLEAR : Watch Dog Timer reset bit PS[2:0] : Overflow period select bits System Control Register (SCONF, 0BFH) WDR : Watch Dog Timer Reset. When system reset by Watch Dog Timer overflow, WDR will be set to 1 ALEI : ALE output inhibit bit, to reduce EMI Setting bit 0 (ALEI) of SCONF can inhibit the clock signal in Fosc/6Hz output to the ALE pin. The bit 7 (WDR) of SCONF is Watch Dog Timer Reset bit. It will be set to 1 when reset signal generated by WDT overflow. User should check WDR bit whenever unpredicted reset happened. 2. Reduce EMI Function The SM79108 allows user to reduce the EMI emission by setting 1 to the bit 0 (ALEI) of SCONF register. This function will inhibit the clock signal in Fosc/6Hz output to the ALE pin. bit-7 bit-0 WDTE R CLEAR Unused Unused PS2 PS1 PS0 Read / Write: R/W - R/W - - R/W R/W R/W Reset value: 000 * * 000 PS [2:0] Overflow Period (ms) 000 2.048 001 4.096 010 8.192 011 16.384 100 32.768 101 65.536 110 131.072 111 262.144 bit-7 bit-0 WDR Unused Unused Unused Unused Reserved Unused ALEI Read / Write: R/W - - - - - - R/W Reset value: 0 **** * * 0 |
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