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SC16C852VIBS Datasheet(PDF) 11 Page - NXP Semiconductors |
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SC16C852VIBS Datasheet(HTML) 11 Page - NXP Semiconductors |
11 / 54 page SC16C852V_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 15 October 2007 11 of 54 NXP Semiconductors SC16C852V Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface [2] These registers are accessible only when LCR[7] is a logic 1. [3] Second Special register are accessible only when EFCR[0] = 1. [4] Enhanced Feature Registers are only accessible when LCR = 0xBF. [5] First Extra Feature Registers are only accessible when EFCR[2:1] = 01b. [6] Second Extra Feature Registers are only accessible when EFCR[2:1] = 10b. 6.4 FIFO operation 6.4.1 32-byte FIFO mode When all four of these registers (TXINTLVL, RXINTLVL, FLWCNTH, FLWCNTL) in the First Extra Register Set are empty (0x00) the transmit and receive trigger levels are set by FCR[7:4]. In this mode the transmit and receive trigger levels are backward compatible to the SC16C652B (see Table 5), and the FIFO sizes are 32 entries. The transmit and receive data FIFOs are enabled by the FIFO Control Register bit 0 (FCR[0]). It should be noted that the user can set the transmit trigger levels by writing to the FCR, but activation will not take place until EFR[4] is set to a logic 1. The receiver FIFO section includes a time-out function to ensure data is delivered to the external CPU (see Section 6.8). Please refer to Table 12 and Table 13 for the setting of FCR[7:4]. 6.4.2 128-byte FIFO mode When either TXINTLVL, RXINTLVL, FLWCNTH or FLWCNTL in the First Extra Register Set contains any value other than 0x00, the transmit and receive trigger levels are set by TXINTLVL and RXINTLVL registers. TXINTLVL sets the trigger levels for the transmit FIFO, and the transmit trigger levels can be set to any value between 1 and 128 with granularity of 1. RXINTLVL sets the trigger levels for the receive FIFO, the receive trigger levels can be set to any value between 1 and 128 with granularity of 1. When the effective FIFO size changes (that is, when FCR[0] toggles or when the combined content of TXINTLVL, RXINTLVL, FLWCNTH and FLWCNTL changes between equal and unequal to 0x00), both RX FIFO and TX FIFO will be reset (data in the FIFO will be lost). 6.5 Hardware flow control When automatic hardware flow control is enabled, the SC16C852V monitors the CTSx pin for a remote buffer overflow indication and controls the RTSx pin for local buffer overflows. Automatic hardware flow control is selected by setting EFR[6] (RTS) and EFR[7] (CTS) to a logic 1. If CTSx transitions from a logic 0 to a logic 1 indicating a flow control request, ISR[5] will be set to a logic 1 (if enabled via IER[7:6]), and the SC16C852V will suspend TX transmissions as soon as the stop bit of the character in process is shifted out. Transmission is resumed after the CTSx input returns to a logic 0, indicating more data may be sent. Table 5. Interrupt trigger level and Flow control mechanism (FCR[7:6, 5:4]) INTA/INTB pin activation Negate RTSA/RTSB or send Xoff Assert RTSA/RTSB or send Xon RX TX [00, 00] 8 16 8 0 [01, 01] 16 8 16 7 [10, 10] 24 24 24 15 [11, 11] 28 30 28 23 |
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