Flexible & Versatile PCI Express

Features

PEX 8524V General Features

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24-lane PCI Express switch

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Integrated SerDes

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Up to six configurable ports

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35mm x35mm, 680 pin PBGA package

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Typical Power: 5.7 Watts

PEX 8524V Key Features

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Standard Compliant

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PCI Express Base Specification, r1.1

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High Performance

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Non-blocking switch fabric

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Full line rate on all ports

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Non-Transparent Bridging

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Configurable Non-Transparent port

for Multi-Host or Intelligent I/O

Support

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Flexible Configuration

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Six highly flexible & configurable

ports (x1, x2, x4, x8, or x16)

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Configurable with strapping pins,

EEPROM, or Host software

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Lane and polarity reversal

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PCI Express Power Management

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Link power management states: L0,

L0s, L1, L2/L3 Ready, and L3

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Device states: D0 and D3hot

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Quality of Service (QoS)

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Two Virtual Channels per port

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Eight Traffic Classes per port

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Fixed and Round-Robin Virtual

Channel Port Arbitration

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Reliability, Availability,

Serviceability

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6 Standard Hot-Plug Controllers

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Upstream port as hot-plug client

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Transaction Layer end-to-end CRC

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Poison bit

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Advanced Error Reporting

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Lane Status bits and GPO available

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Per port performance monitoring

• Average packet size

• Number of packets

• CRC errors and more

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JTAG boundary scan

Multi-purpose, Feature Rich ExpressLane™ PCI Express Switch

The ExpressLane PEX 8524V device offers PCI Express switching capability

enabling users to add scalable high bandwidth, non-blocking interconnection to a

wide variety of applications including servers, storage systems, communications

platforms, blade servers, and embedded-control products. The PEX 8524V is

well suited for fan-out, aggregation, dual-graphics, peer-to-peer, and intelligent

I/O module applications.

Highly Flexible Port Configurations

The ExpressLane PEX 8524V offers highly configurable ports. There are a

maximum of 6 ports that can be configured to any legal width from x1 to x16, in any

combination to support your specific bandwidth needs. The ports can be configured

for symmetric (each port having the same lane width and traffic load) or

asymmetric (ports having different lane widths) traffic. In the event of asymmetric

traffic, the PEX 8524V features a flexible central packet memory that allocates a

memory buffer for each port as required by the application or endpoint. This buffer

allocation along with the device's flexible packet flow control minimizes

bottlenecks when the upstream and aggregated downstream bandwidths do not match

(are asymmetric). Any of the ports can be designated as the upstream port, which can

be changed dynamically.

End-to-end Packet Integrity

The PEX 8524V provides end-to-end CRC protection (ECRC) and Poison bit

support to enable designs that require end-to-end data integrity. These features are

optional in the PCI Express specification, but PLX provides them across its entire

ExpressLane switch product line.

Non-Transparent “Bridging” in a PCI Express Switch

The ExpressLane PEX 8524V product supports full non-transparent bridging (NTB)

functionality to allow implementation of multi-host systems and intelligent I/O

modules in communications, storage, blade server, and graphics fan-out

applications. To ensure quick product migration, the non-transparency features are

implemented in the same fashion as in standard PCI applications.

Non-transparent bridges allow systems to isolate memory domains by presenting the

processor subsystem as an endpoint, rather than another memory system. Base

address registers are used to translate addresses; doorbell registers are used to send

interrupts between the address domains; and scratchpad registers are accessible from

both address domains to allow inter-processor communication.

Two Virtual Channels

The ExpressLane PEX 8524V switch supports 2 full-featured Virtual Channels

(VCs) and a full 8 Traffic Classes (TCs). The mapping of Traffic Classes to port-

specific Virtual Channels allows for different mappings for different ports. In

addition, the devices offer user-selectable Virtual Channel arbitration algorithms to

enable users to fine tune the Quality of Service (QoS) required for a specific

application.

Low Power with Granular SerDes Control

The PEX 8524V provides low power capability that is fully compliant with the PCI

Express power management specification. In addition, the SerDes physical links can

be turned off when unused for even lower power.

PEX 8524V

Version 1.4 2007