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FDMF8704 Rev. F2

Module Power Loss Measurement and

Calculation

Refer to Figure 18 for module power loss testing method. Power

loss calculation are as follows:

PCB Layout Guideline

Figure 19. shows a proper layout example of FDMF8704 and

stable current flow, heat radiation and system performance.

Following is a guideline which the PCB designer should

consider:

of FDMF8704 to help reduce input current ripple component

induced by switching operation.

2. It is critical that the VSWH copper has minimum area for

lower switching noise emission. VSWH copper trace should

also be wide enough for high current flow. Other signal routing

path, such as PWM IN and BOOT signal, should be considered

with care to avoid noise pickup from VSWH copper area.

3. Output inductor location should be as close as possible to the

FDMF8704 for lower power loss due to copper trace.

4. Snubber for suppressing ringing and spiking of VSWH

voltage should be placed near the FDMF8704. The resistor and

capacitor need to be of proper size for power dissipation.

5. Place boot diode, ceramic bypass capacitor and boot

to supply stable power. Routing width and length should also be

considered

6. Use multiple Vias on each copper area to interconnect each

top, inner and bottom layer to help smooth current flow and heat

conduction. Vias should be relatively large and of reasonable

inductance.

DISB

PWM

CGND PGND

VIN

VCIN

VSWH

DISB

PWM

Input

BOOT

A

A

A

Figure 18. Power Loss Measurement Block Diagram

Figure 19. Typical PCB Layout Example (Top View)

HSEN

L