EDE1116ABSE-5C-E datasheet(76/82 Pages) ELPIDA

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EDE1116ABSE-5C-E Datasheet(PDF) 76 Page - Elpida Memory

76 / 82 page

EDE1104ABSE, EDE1108ABSE, EDE1116ABSE

Data Sheet E0852E50 (Ver. 5.0)

Asynchronous CKE Low Event

DRAM requires CKE to be maintained high for all valid operations as defined in this data sheet.

If CKE

asynchronously drops low during any valid operation DRAM is not guaranteed to preserve the contents of array. If

this event occurs, memory controller must satisfy DRAM timing specification tDELAY before turning off the clocks.

Stable clocks must exist at the input of DRAM before CKE is raised high again. DRAM must be fully re-initialized

(steps 4 through 13) as described in initialization sequence.

DRAM is ready for normal operation after the

initialization sequence. See AC Characteristics table for tDELAY specification

tCK

/CK

tDELAY

CKE

CKE asynchronously

drops low

Clocks can be

turned off after

this point

Stable clocks

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