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EDE1116ABSE-6E-E Datasheet(PDF) 39 Page - Elpida Memory |
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EDE1116ABSE-6E-E Datasheet(HTML) 39 Page - Elpida Memory |
39 / 82 page EDE1104ABSE, EDE1108ABSE, EDE1116ABSE Data Sheet E0852E50 (Ver. 5.0) 39 8. The minimum delay from the read, write and precharge command to the precharge command to the same bank is summarized below. [Precharge and Auto Precharge Clarification] From command To command Minimum delay between “From command” to “To Command“ Units Notes Read Precharge (to same bank as read) AL + (BL/2) + Max.(RTP, 2) − 2 tCK a, b Precharge all AL + (BL/2) + Max.(RTP, 2) − 2 tCK a, b Read w/AP Precharge (to same bank as read w/AP) AL + (BL/2) + Max.(RTP, 2) − 2 tCK a, b Precharge all AL + (BL/2) + Max.(RTP, 2) − 2 tCK a, b Write Precharge (to same bank as write) WL + (BL/2) + tWR tCK b Precharge all WL + (BL/2) + tWR tCK b Write w/AP Precharge (to same bank as write w/AP) WL + (BL/2) + WR tCK b Precharge all WL + (BL/2) + WR tCK b Precharge Precharge (to same bank as precharge) 1 tCK b Precharge all 1 tCK b Precharge all Precharge 1 tCK b Precharge all 1 tCK b a. RTP[cycles] = RU{ tRTP[ns] / tCK[ns] }, where RU stands for round up. tCK(avg) should be used in place of tCK for DDR2-667/800. b. For a given bank, the precharge period should be counted from the latest precharge command, either one bank precharge or precharge all, issued to that bank. The precharge period is satisfied after tRP depending on the latest precharge command issued to that bank. |
Similar Part No. - EDE1116ABSE-6E-E |
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