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EDE1116ABSE-6E-E Datasheet(PDF) 52 Page - Elpida Memory |
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EDE1116ABSE-6E-E Datasheet(HTML) 52 Page - Elpida Memory |
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52 / 82 page  EDE1104ABSE, EDE1108ABSE, EDE1116ABSE Data Sheet E0852E50 (Ver. 5.0) 52 Bank Activate Command [ACT] The bank activate command is issued by holding /CAS and /WE high with /CS and /RAS low at the rising edge of the clock. The bank addresses BA0, BA1 and BA2 are used to select the desired bank. The row address A0 through A13 is used to determine which row to activate in the selected bank. The Bank activate command must be applied before any read or write operation can be executed. Immediately after the bank active command, the DDR2 SDRAM can accept a read or write command on the following clock cycle. If a R/W command is issued to a bank that has not satisfied the tRCD (min.) specification, then additive latency must be programmed into the device to delay when the R/W command is internally issued to the device. The additive latency value must be chosen to assure tRCD (min.) is satisfied. Additive latencies of 0, 1, 2, 3 and 4 are supported. Once a bank has been activated it must be precharged before another bank activate command can be applied to the same bank. The bank active and precharge times are defined as tRAS and tRP, respectively. The minimum time interval between successive bank activate commands to the same bank is determined by the /RAS cycle time of the device (tRC), which is equal to tRAS + tRP. The minimum time interval between successive bank activate commands to the different bank is determined by (tRRD). In order to ensure that 8-bank devices do not exceed the instantaneous current supplying capability of 4-bank devices, a restriction on the number of sequential ACT commands that can be issued must be observed. The rule is as follows: Note: 8-bank device sequential bank activation restriction: No more than 4 banks may be activated in a rolling tFAW window. Converting to clocks is done by dividing tFAW (ns) by tCK (ns) and rounding up to next integer value. As an example of the rolling window, if (tFAW/tCK) rounds up to 10 clocks, and an activate command is issued in clock N, no more than three further activate commands may be issued in clock N+1 through N+9. /CK CK Address Command T0 T1 T2 T3 Tn Tn+1 Tn+2 Tn+3 tRCD(min.) tRAS tRP tRC ROW: 0 ACT Bank0 Active Bank1 Active Bank0 Active Bank0 Precharge Bank1 Precharge Posted READ Posted READ ACT PRE PRE ACT COL: 0 ROW: 0 ROW: 1 COL: 1 tCCD Additive latency (AL) tRRD Bank0 Read begins Bank Activate Command Cycle (tRCD = 3, AL = 2, tRP = 3, tRRD = 2, tCCD = 2) |
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