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EDE1116ABSE Datasheet(PDF) 53 Page - Elpida Memory |
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EDE1116ABSE Datasheet(HTML) 53 Page - Elpida Memory |
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53 / 82 page  EDE1104ABSE, EDE1108ABSE, EDE1116ABSE Data Sheet E0852E50 (Ver. 5.0) 53 Read and Write Access Modes After a bank has been activated, a read or write cycle can be executed. This is accomplished by setting /RAS high, /CS and /CAS low at the clock’s rising edge. /WE must also be defined at this time to determine whether the access cycle is a read operation (/WE high) or a write operation (/WE low). The DDR2 SDRAM provides a fast column access operation. A single read or write command will initiate a serial read or write operation on successive clock cycles. The boundary of the burst cycle is strictly restricted to specific segments of the page length. For example, the 32M bits × 4 I/O × 8 banks chip has a page length of 2048 bits (defined by CA0 to CA9, CA11). The page length of 2048 is divided into 512 uniquely addressable boundary segments (4 bits each). A 4 bits burst operation will occur entirely within one of the 512 groups beginning with the column address supplied to the device during the read or write command (CA0 to CA9, CA11). The second, third and fourth access will also occur within this group segment, however, the burst order is a function of the starting address, and the burst sequence. A new burst access must not interrupt the previous 4-bit burst operation. The minimum /CAS to /CAS delay is defined by tCCD, and is a minimum of 2 clocks for read or write cycles. Posted /CAS Posted /CAS operation is supported to make command and data bus efficient for sustainable bandwidths in DDR2 SDRAM. In this operation, the DDR2 SDRAM allows a /CAS read or write command to be issued immediately after the /RAS bank activate command (or any time during the /RAS-/CAS-delay time, tRCD, period). The command is held for the time of the Additive Latency (AL) before it is issued inside the device. The Read Latency (RL) is controlled by the sum of AL and the /CAS latency (CL). Therefore if a user chooses to issue a R/W command before the tRCD (min), then AL (greater than 0) must be written into the EMRS. The Write Latency (WL) is always defined as RL − 1 (read latency −1) where read latency is defined as the sum of additive latency plus /CAS latency (RL = AL + CL). -1 /CK CK DQS, /DQS AL = 2 ≥ tRCD ≥ tRAC CL = 3 Command DQ 0123456789 10 11 12 ACT READ NOP NOP WRIT out0 out1 out2 out3 in0 in1 in2 in3 WL = RL – 1 = 4 RL = AL + CL = 5 Read Followed by a Write to the Same Bank [AL = 2 and CL = 3, RL = (AL + CL) = 5, WL = (RL - 1) = 4] -1 0123456789 10 11 12 /CK DQS, /DQS AL = 0 ≥ tRCD ≥ tRAC CL = 3 Command DQ ACT READ WRIT out0 out1 out2 out3 in0 in1 in2 in3 CK RL = AL + CL = 3 WL = RL – 1 = 2 NOP NOP NOP Read Followed by a Write to the Same Bank [AL = 0 and CL = 3, RL = (AL + CL) = 3, WL = (RL - 1) = 2] |
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